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From: Lyude Paul <lyude@redhat.com>
To: Imre Deak <imre.deak@intel.com>, intel-gfx@lists.freedesktop.org
Cc: Ville Syrjala <ville.syrjala@intel.com>,
	dri-devel@lists.freedesktop.org, stable@vger.kernel.org
Subject: Re: [Intel-gfx] [PATCH 1/2] drm/dp/mst: Export drm_dp_get_vc_payload_bw()
Date: Mon, 25 Jan 2021 14:22:26 -0500	[thread overview]
Message-ID: <8780f792b606558ac501ce1d9b281d0da76a177b.camel@redhat.com> (raw)
In-Reply-To: <20210125173636.1733812-1-imre.deak@intel.com>

On Mon, 2021-01-25 at 19:36 +0200, Imre Deak wrote:
> This function will be needed by the next patch where the driver
> calculates the BW based on driver specific parameters, so export it.
> 
> At the same time sanitize the function params, passing the more natural
> link rate instead of the encoding of the same rate.
> 
> Cc: Lyude Paul <lyude@redhat.com>
> Cc: Ville Syrjala <ville.syrjala@intel.com>
> Cc: <stable@vger.kernel.org>
> Cc: dri-devel@lists.freedesktop.org
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/drm_dp_mst_topology.c | 24 ++++++++++++++++++------
>  include/drm/drm_dp_mst_helper.h       |  1 +
>  2 files changed, 19 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
> b/drivers/gpu/drm/drm_dp_mst_topology.c
> index 475939138b21..dc96cbf78cc6 100644
> --- a/drivers/gpu/drm/drm_dp_mst_topology.c
> +++ b/drivers/gpu/drm/drm_dp_mst_topology.c
> @@ -3629,14 +3629,26 @@ static int drm_dp_send_up_ack_reply(struct
> drm_dp_mst_topology_mgr *mgr,
>         return 0;
>  }
>  
> -static int drm_dp_get_vc_payload_bw(u8 dp_link_bw, u8  dp_link_count)
> +/**
> + * drm_dp_get_vc_payload_bw - get the VC payload BW for an MST link
> + * @rate: link rate in 10kbits/s units
> + * @lane_count: lane count
> + *
> + * Calculate the toal bandwidth of a MultiStream Transport link. The returned

s/toal/total/

With that fixed, this patch is:

Reviewed-by: Lyude Paul <lyude@redhat.com>

> + * value is in units of PBNs/(timeslots/1 MTP). This value can be used to
> + * convert the number of PBNs required for a given stream to the number of
> + * timeslots this stream requires in each MTP.
> + */
> +int drm_dp_get_vc_payload_bw(int link_rate, int link_lane_count)
>  {
> -       if (dp_link_bw == 0 || dp_link_count == 0)
> -               DRM_DEBUG_KMS("invalid link bandwidth in DPCD: %x (link count:
> %d)\n",
> -                             dp_link_bw, dp_link_count);
> +       if (link_rate == 0 || link_lane_count == 0)
> +               DRM_DEBUG_KMS("invalid link rate/lane count: (%d / %d)\n",
> +                             link_rate, link_lane_count);
>  
> -       return dp_link_bw * dp_link_count / 2;
> +       /* See DP v2.0 2.6.4.2,
> VCPayload_Bandwidth_for_OneTimeSlotPer_MTP_Allocation */
> +       return link_rate * link_lane_count / 54000;
>  }
> +EXPORT_SYMBOL(drm_dp_get_vc_payload_bw);
>  
>  /**
>   * drm_dp_read_mst_cap() - check whether or not a sink supports MST
> @@ -3692,7 +3704,7 @@ int drm_dp_mst_topology_mgr_set_mst(struct
> drm_dp_mst_topology_mgr *mgr, bool ms
>                         goto out_unlock;
>                 }
>  
> -               mgr->pbn_div = drm_dp_get_vc_payload_bw(mgr->dpcd[1],
> +               mgr->pbn_div =
> drm_dp_get_vc_payload_bw(drm_dp_bw_code_to_link_rate(mgr->dpcd[1]),
>                                                         mgr->dpcd[2] &
> DP_MAX_LANE_COUNT_MASK);
>                 if (mgr->pbn_div == 0) {
>                         ret = -EINVAL;
> diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h
> index f5e92fe9151c..bd1c39907b92 100644
> --- a/include/drm/drm_dp_mst_helper.h
> +++ b/include/drm/drm_dp_mst_helper.h
> @@ -783,6 +783,7 @@ drm_dp_mst_detect_port(struct drm_connector *connector,
>  
>  struct edid *drm_dp_mst_get_edid(struct drm_connector *connector, struct
> drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port);
>  
> +int drm_dp_get_vc_payload_bw(int link_rate, int link_lane_count);
>  
>  int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc);
>  

-- 
Sincerely,
   Lyude Paul (she/her)
   Software Engineer at Red Hat
   
Note: I deal with a lot of emails and have a lot of bugs on my plate. If you've
asked me a question, are waiting for a review/merge on a patch, etc. and I
haven't responded in a while, please feel free to send me another email to check
on my status. I don't bite!

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  parent reply	other threads:[~2021-01-25 19:22 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-25 17:36 [Intel-gfx] [PATCH 1/2] drm/dp/mst: Export drm_dp_get_vc_payload_bw() Imre Deak
2021-01-25 17:36 ` [Intel-gfx] [PATCH 2/2] drm/i915: Fix the MST PBN divider calculation Imre Deak
2021-01-25 19:24   ` Lyude Paul
2021-01-25 21:04     ` Imre Deak
2021-01-25 22:55       ` Lyude Paul
2021-01-26 12:06         ` Imre Deak
2021-01-28 13:54   ` Ville Syrjälä
2021-01-25 19:22 ` Lyude Paul [this message]
2021-01-25 19:25 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/dp/mst: Export drm_dp_get_vc_payload_bw() Patchwork
2021-01-25 19:27 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-01-25 19:56 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-01-26  1:28 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-01-28 19:38   ` Imre Deak

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