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From: Jani Nikula <jani.nikula@linux.intel.com>
To: Lucas De Marchi <lucas.demarchi@intel.com>,
	Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Cc: intel-gfx@lists.freedesktop.org, ville.syrjala@intel.com
Subject: Re: [Intel-gfx] [RFC v4 1/2] drm/i915: Add RPL-U sub platform
Date: Mon, 20 Nov 2023 12:30:57 +0200	[thread overview]
Message-ID: <878r6spvha.fsf@intel.com> (raw)
In-Reply-To: <qttczeukv7fu4dnq3rh7xua5vimhhu6kfqwhqbf3aes2aze5ty@pejh24rjpnvk>

On Fri, 17 Nov 2023, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> On Mon, Jan 30, 2023 at 03:38:05PM +0530, Chaitanya Kumar Borah wrote:
>>Separate out RPLU device ids and add them to both RPL and
>>newly created RPL-U subplatforms.
>>
>>v2: (Matt)
>>    - Sort PCI-IDs numerically
>>    - Name the sub-platform to accurately depict what it is for
>>    - Make RPL-U part of RPL subplatform
>>
>>v3: revert to RPL-U subplatform (Jani)
>>
>>v4: (Jani)
>>    - Add RPL-U ids to RPL-P platform
>
> humn...
>
>>diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
>>index 4a4c190f7698..5824e1d7d162 100644
>>--- a/include/drm/i915_pciids.h
>>+++ b/include/drm/i915_pciids.h
>>@@ -684,14 +684,18 @@
>> 	INTEL_VGA_DEVICE(0xA78A, info), \
>> 	INTEL_VGA_DEVICE(0xA78B, info)
>>
>>+/* RPL-U */
>>+#define INTEL_RPLU_IDS(info) \
>>+	INTEL_VGA_DEVICE(0xA721, info), \
>>+	INTEL_VGA_DEVICE(0xA7A1, info), \
>>+	INTEL_VGA_DEVICE(0xA7A9, info)
>>+
>> /* RPL-P */
>> #define INTEL_RPLP_IDS(info) \
>>+	INTEL_RPLU_IDS(info), \
>
> drive by comment while reviewing other stuff. Why was U added to the
> P macro? That looks odd. Adding it to the rpl subplatform, together with P would
> be ok, but in this macro it looks wrong. Doing it the other way I think the
> only affected place would be the early-quirks, which would need a separate entry,
> but admitedly they should had been INTEL_RPL_IDS() with all the
> variants.

It's been 10 months, I have no recollection, but this is what I found in
old mails [1].

BR,
Jani.

[1] https://lore.kernel.org/r/87mt686m1o.fsf@intel.com

>
>
> Lucas De Marchi

-- 
Jani Nikula, Intel

  reply	other threads:[~2023-11-20 10:31 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-30 10:08 [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U Chaitanya Kumar Borah
2023-01-30 10:08 ` [Intel-gfx] [RFC v4 1/2] drm/i915: Add RPL-U sub platform Chaitanya Kumar Borah
2023-11-17 23:35   ` Lucas De Marchi
2023-11-20 10:30     ` Jani Nikula [this message]
2023-01-30 10:08 ` [Intel-gfx] [RFC v4 2/2] drm/i915/display: Add 480 MHz CDCLK steps for RPL-U Chaitanya Kumar Borah
2023-01-30 11:32 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add new CDCLK step for RPL-U (rev6) Patchwork
2023-01-30 11:44 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-01-30 14:05 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2023-02-16 10:52 ` [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U Jani Nikula
2023-02-28  0:35 ` Matt Roper
2023-02-28 10:42   ` Borah, Chaitanya Kumar

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