From: Jani Nikula <jani.nikula@linux.intel.com>
To: Gustavo Sousa <gustavo.sousa@intel.com>,
Khaled Almahallawy <khaled.almahallawy@intel.com>,
intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] drm/i915/cx0: Only clear/set the Pipe Reset bit of the PHY Lanes Owned
Date: Thu, 05 Oct 2023 16:16:33 +0300 [thread overview]
Message-ID: <878r8hciq6.fsf@intel.com> (raw)
In-Reply-To: <169650959377.1601.4111271359854746928@gjsousa-mobl2>
On Thu, 05 Oct 2023, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
> Quoting Khaled Almahallawy (2023-10-04 21:13:10-03:00)
>>Currently, with MFD/pin assignment D, the driver clears the pipe reset bit
>>of lane 1 which is not owned by display. This causes the display
>>to block S0iX.
>>
>>By not clearing this bit for lane 1 and keeping whatever default, S0ix
>>started to work. This is already what the driver does at the end
>>of the phy lane reset sequence (Step#8)
>>
>>Bspec: 65451
>>
>
> We should not have blank lines in the trailers section. This could be fixed
> while applying.
Agreed.
>
>>Cc: Mika Kahola <mika.kahola@intel.com>
>>Cc: Gustavo Sousa <gustavo.sousa@intel.com>
>>Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com>
>
> Nice fix. Thanks!
>
> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
>
>>---
>> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 3 +--
>> 1 file changed, 1 insertion(+), 2 deletions(-)
>>
>>diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>>index abd607b564f1..f653b83a7d4f 100644
>>--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>>+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>>@@ -2596,8 +2596,7 @@ static void intel_cx0_phy_lane_reset(struct drm_i915_private *i915,
>> drm_warn(&i915->drm, "PHY %c failed to bring out of SOC reset after %dus.\n",
>> phy_name(phy), XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US);
>>
>>- intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
>>- XELPDP_LANE_PIPE_RESET(0) | XELPDP_LANE_PIPE_RESET(1),
>>+ intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port), lane_pipe_reset,
>> lane_pipe_reset);
>>
>> if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL2(port),
>>--
>>2.25.1
>>
--
Jani Nikula, Intel
next prev parent reply other threads:[~2023-10-05 13:22 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-05 0:13 [Intel-gfx] [PATCH] drm/i915/cx0: Only clear/set the Pipe Reset bit of the PHY Lanes Owned Khaled Almahallawy
2023-10-05 4:17 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2023-10-05 12:39 ` [Intel-gfx] [PATCH] " Gustavo Sousa
2023-10-05 13:16 ` Jani Nikula [this message]
2023-10-11 20:32 ` Sripada, Radhakrishna
2023-10-05 15:03 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=878r8hciq6.fsf@intel.com \
--to=jani.nikula@linux.intel.com \
--cc=gustavo.sousa@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=khaled.almahallawy@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox