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From: Jani Nikula <jani.nikula@linux.intel.com>
To: "Hans de Goede" <hdegoede@redhat.com>,
	"Joonas Lahtinen" <joonas.lahtinen@linux.intel.com>,
	"Rodrigo Vivi" <rodrigo.vivi@intel.com>,
	"Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: Hans de Goede <hdegoede@redhat.com>,
	intel-gfx <intel-gfx@lists.freedesktop.org>,
	dri-devel@lists.freedesktop.org,
	Tsuchiya Yuto <kitakar@gmail.com>
Subject: Re: [Intel-gfx] [PATCH] drm/i915/vlv_dsi: Double pixelclock on read-back for dual-link panels
Date: Mon, 25 Oct 2021 11:17:42 +0300	[thread overview]
Message-ID: <87a6ixldqx.fsf@intel.com> (raw)
In-Reply-To: <20211024155020.126328-1-hdegoede@redhat.com>

On Sun, 24 Oct 2021, Hans de Goede <hdegoede@redhat.com> wrote:
> In intel_dsi_get_config() double the pclk returned by foo_dsi_get_pclk()
> for dual-link panels. This fixes the following WARN triggering:
>
>  i915 0000:00:02.0: [drm] *ERROR* [CRTC:51:pipe A] mismatch in pixel_rate (expected 235710, found 118056)
>  i915 0000:00:02.0: [drm] *ERROR* [CRTC:51:pipe A] mismatch in hw.pipe_mode.crtc_clock (expected 235710, found 118056)
>  i915 0000:00:02.0: [drm] *ERROR* [CRTC:51:pipe A] mismatch in hw.adjusted_mode.crtc_clock (expected 235710, found 118056)
>  i915 0000:00:02.0: [drm] *ERROR* [CRTC:51:pipe A] mismatch in port_clock (expected 235710, found 118056)
>  ------------[ cut here ]------------
>  pipe state doesn't match!
>  WARNING: CPU: 3 PID: 136 at drivers/gpu/drm/i915/display/intel_display.c:9125 intel_display_finish_reset+0x1bd3/0x2050 [i915]
>  ...
>
> This has been tested on a Xiaomi Mi Pad 2 (with CHT x5-Z8500 SoC) tablet,
> with a 1536x2048 dual-link DSI panel.
>
> Note this fix was taken from icl_dsi.c which does the same in
> its get_config().
>
> Cc: Tsuchiya Yuto <kitakar@gmail.com>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>

Acked-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/vlv_dsi.c | 5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
> index 3e646a58b38a..2b7909bc52ff 100644
> --- a/drivers/gpu/drm/i915/display/vlv_dsi.c
> +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
> @@ -1265,7 +1265,9 @@ static void intel_dsi_get_config(struct intel_encoder *encoder,
>  				 struct intel_crtc_state *pipe_config)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
>  	u32 pclk;
> +
>  	drm_dbg_kms(&dev_priv->drm, "\n");
>  
>  	pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
> @@ -1277,6 +1279,9 @@ static void intel_dsi_get_config(struct intel_encoder *encoder,
>  		pclk = vlv_dsi_get_pclk(encoder, pipe_config);
>  	}
>  
> +	if (intel_dsi->dual_link)
> +		pclk *= 2;
> +
>  	if (pclk) {
>  		pipe_config->hw.adjusted_mode.crtc_clock = pclk;
>  		pipe_config->port_clock = pclk;

-- 
Jani Nikula, Intel Open Source Graphics Center

  parent reply	other threads:[~2021-10-25  8:17 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-24 15:50 [Intel-gfx] [PATCH] drm/i915/vlv_dsi: Double pixelclock on read-back for dual-link panels Hans de Goede
2021-10-24 16:34 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2021-10-24 17:00 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-10-24 18:26 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-10-25  8:17 ` Jani Nikula [this message]
2021-11-18 11:55   ` [Intel-gfx] [PATCH] " Hans de Goede

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