From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To: Radhakrishna Sripada <radhakrishna.sripada@intel.com>,
intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v2 5/6] drm/i915/icl: Add Wa_1406609255
Date: Tue, 09 Oct 2018 10:18:53 +0300 [thread overview]
Message-ID: <87a7nnk2oy.fsf@gaia.fi.intel.com> (raw)
In-Reply-To: <20181004182939.7668-5-radhakrishna.sripada@intel.com>
Radhakrishna Sripada <radhakrishna.sripada@intel.com> writes:
> Shader feature to prefetch binding tables does not support 16:6 18:8 BTP
> formats. Enabling fault handling could result in hangs with faults.
> Disabling demand prefetch would disable binding table prefetch.
>
> V2: Fix the stepping rivision to B0(Mika)
>
> References: HSDES#1406609255, HSDES#1406573985
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Pushed, thanks for the patch.
-Mika
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> drivers/gpu/drm/i915/intel_workarounds.c | 6 ++++++
> 2 files changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c8a187d8db0f..fa020425754f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7413,6 +7413,9 @@ enum {
> #define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
> #define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11)
>
> +#define GEN7_SARCHKMD _MMIO(0xB000)
> +#define GEN7_DISABLE_DEMAND_PREFETCH (1 << 31)
> +
> #define GEN7_L3SQCREG1 _MMIO(0xB010)
> #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
>
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index 65cd36cd2957..cf4f4c1f86ab 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -905,6 +905,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> I915_WRITE(GAMT_CHKN_BIT_REG,
> I915_READ(GAMT_CHKN_BIT_REG) |
> GAMT_CHKN_DISABLE_L3_COH_PIPE);
> +
> + /* Wa_1406609255:icl (pre-prod) */
> + if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
> + I915_WRITE(GEN7_SARCHKMD,
> + I915_READ(GEN7_SARCHKMD) |
> + GEN7_DISABLE_DEMAND_PREFETCH);
> }
>
> void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> --
> 2.9.3
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next prev parent reply other threads:[~2018-10-09 7:19 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-04 18:29 [PATCH v2 1/6] drm/i915/icl: Add WaEnable32PlaneMode Radhakrishna Sripada
2018-10-04 18:29 ` [PATCH v2 2/6] drm/i915/icl: Implement Display WA_1405510057 Radhakrishna Sripada
2018-10-17 21:49 ` Srivatsa, Anusha
2018-10-04 18:29 ` [PATCH v2 3/6] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7 Radhakrishna Sripada
2018-10-12 19:01 ` Radhakrishna Sripada
2018-10-04 18:29 ` [PATCH v2 4/6] drm/i915/icl: WaAllowUMDToModifySamplerMode Radhakrishna Sripada
2018-10-12 18:58 ` Radhakrishna Sripada
2018-10-04 18:29 ` [PATCH v2 5/6] drm/i915/icl: Add Wa_1406609255 Radhakrishna Sripada
2018-10-08 13:55 ` Mika Kuoppala
2018-10-09 7:18 ` Mika Kuoppala [this message]
2018-10-04 18:29 ` [PATCH v2 6/6] drm/i915/icl:Add Wa_1606682166 Radhakrishna Sripada
2018-10-08 14:02 ` Mika Kuoppala
2018-10-09 7:19 ` Mika Kuoppala
2018-10-04 19:08 ` ✓ Fi.CI.BAT: success for series starting with [v2,1/6] drm/i915/icl: Add WaEnable32PlaneMode Patchwork
2018-10-05 2:32 ` ✓ Fi.CI.IGT: " Patchwork
2018-10-17 22:13 ` [PATCH v2 1/6] " Srivatsa, Anusha
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