From: Jani Nikula <jani.nikula@intel.com>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Subject: Re: [PATCH 06/11] drm/i915/reg: fix PCH transcoder timing and data/link m/n style
Date: Tue, 10 Sep 2024 11:05:10 +0300 [thread overview]
Message-ID: <87bk0wkk7d.fsf@intel.com> (raw)
In-Reply-To: <Zt9iNpF3mYjzdKUQ@intel.com>
On Tue, 10 Sep 2024, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Mon, Sep 09, 2024 at 09:58:57PM +0300, Jani Nikula wrote:
>> Adhere to the style described at the top of i915_reg.h.
>>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 77 ++++++++++++++++++---------------
>> 1 file changed, 43 insertions(+), 34 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 2f09145b9791..e439a67fde61 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -3160,33 +3160,76 @@
>> /* transcoder */
>>
>> #define _PCH_TRANS_HTOTAL_A 0xe0000
>> +#define _PCH_TRANS_HTOTAL_B 0xe1000
>
> There's some tab vs. space damage in this patch.
Ah, the damage is there before, and I'm just moving lines around. Fixing
in the same patch breaks git show --color-moved, do you prefer fixing in
the same patch or a separate patch?
BR,
Jani.
>
>> +#define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
>> #define TRANS_HTOTAL_SHIFT 16
>> #define TRANS_HACTIVE_SHIFT 0
>> +
>> #define _PCH_TRANS_HBLANK_A 0xe0004
>> +#define _PCH_TRANS_HBLANK_B 0xe1004
>> +#define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
>> #define TRANS_HBLANK_END_SHIFT 16
>> #define TRANS_HBLANK_START_SHIFT 0
>> +
>> #define _PCH_TRANS_HSYNC_A 0xe0008
>> +#define _PCH_TRANS_HSYNC_B 0xe1008
>> +#define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
>> #define TRANS_HSYNC_END_SHIFT 16
>> #define TRANS_HSYNC_START_SHIFT 0
>> +
>> #define _PCH_TRANS_VTOTAL_A 0xe000c
>> +#define _PCH_TRANS_VTOTAL_B 0xe100c
>> +#define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
>> #define TRANS_VTOTAL_SHIFT 16
>> #define TRANS_VACTIVE_SHIFT 0
>> +
>> #define _PCH_TRANS_VBLANK_A 0xe0010
>> +#define _PCH_TRANS_VBLANK_B 0xe1010
>> +#define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
>> #define TRANS_VBLANK_END_SHIFT 16
>> #define TRANS_VBLANK_START_SHIFT 0
>> +
>> #define _PCH_TRANS_VSYNC_A 0xe0014
>> +#define _PCH_TRANS_VSYNC_B 0xe1014
>> +#define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
>> #define TRANS_VSYNC_END_SHIFT 16
>> #define TRANS_VSYNC_START_SHIFT 0
>> +
>> #define _PCH_TRANS_VSYNCSHIFT_A 0xe0028
>> +#define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
>> +#define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B)
>>
>> #define _PCH_TRANSA_DATA_M1 0xe0030
>> +#define _PCH_TRANSB_DATA_M1 0xe1030
>> +#define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
>> +
>> #define _PCH_TRANSA_DATA_N1 0xe0034
>> +#define _PCH_TRANSB_DATA_N1 0xe1034
>> +#define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
>> +
>> #define _PCH_TRANSA_DATA_M2 0xe0038
>> +#define _PCH_TRANSB_DATA_M2 0xe1038
>> +#define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
>> +
>> #define _PCH_TRANSA_DATA_N2 0xe003c
>> +#define _PCH_TRANSB_DATA_N2 0xe103c
>> +#define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
>> +
>> #define _PCH_TRANSA_LINK_M1 0xe0040
>> +#define _PCH_TRANSB_LINK_M1 0xe1040
>> +#define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
>> +
>> #define _PCH_TRANSA_LINK_N1 0xe0044
>> +#define _PCH_TRANSB_LINK_N1 0xe1044
>> +#define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
>> +
>> #define _PCH_TRANSA_LINK_M2 0xe0048
>> +#define _PCH_TRANSB_LINK_M2 0xe1048
>> +#define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
>> +
>> #define _PCH_TRANSA_LINK_N2 0xe004c
>> +#define _PCH_TRANSB_LINK_N2 0xe104c
>> +#define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
>>
>> /* Per-transcoder DIP controls (PCH) */
>> #define _VIDEO_DIP_CTL_A 0xe0200
>> @@ -3292,40 +3335,6 @@
>>
>> #define HSW_STEREO_3D_CTL(dev_priv, trans) _MMIO_PIPE2(dev_priv, trans, _HSW_STEREO_3D_CTL_A)
>>
>> -#define _PCH_TRANS_HTOTAL_B 0xe1000
>> -#define _PCH_TRANS_HBLANK_B 0xe1004
>> -#define _PCH_TRANS_HSYNC_B 0xe1008
>> -#define _PCH_TRANS_VTOTAL_B 0xe100c
>> -#define _PCH_TRANS_VBLANK_B 0xe1010
>> -#define _PCH_TRANS_VSYNC_B 0xe1014
>> -#define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
>> -
>> -#define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
>> -#define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
>> -#define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
>> -#define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
>> -#define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
>> -#define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
>> -#define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B)
>> -
>> -#define _PCH_TRANSB_DATA_M1 0xe1030
>> -#define _PCH_TRANSB_DATA_N1 0xe1034
>> -#define _PCH_TRANSB_DATA_M2 0xe1038
>> -#define _PCH_TRANSB_DATA_N2 0xe103c
>> -#define _PCH_TRANSB_LINK_M1 0xe1040
>> -#define _PCH_TRANSB_LINK_N1 0xe1044
>> -#define _PCH_TRANSB_LINK_M2 0xe1048
>> -#define _PCH_TRANSB_LINK_N2 0xe104c
>> -
>> -#define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
>> -#define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
>> -#define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
>> -#define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
>> -#define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
>> -#define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
>> -#define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
>> -#define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
>> -
>> #define _PCH_TRANSACONF 0xf0008
>> #define _PCH_TRANSBCONF 0xf1008
>> #define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
>> --
>> 2.39.2
--
Jani Nikula, Intel
next prev parent reply other threads:[~2024-09-10 8:05 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-09 18:58 [PATCH 00/11] drm/i915: split out display regs Jani Nikula
2024-09-09 18:58 ` [PATCH 01/11] drm/i915/reg: fix transcoder timing register style Jani Nikula
2024-09-09 18:58 ` [PATCH 02/11] drm/i915/reg: fix g4x pipe data/link m/n " Jani Nikula
2024-09-09 18:58 ` [PATCH 03/11] drm/i915/reg: fix pipe conf, stat etc. " Jani Nikula
2024-09-09 18:58 ` [PATCH 04/11] drm/i915/reg: fix pipe data/link m/n " Jani Nikula
2024-09-09 18:58 ` [PATCH 05/11] drm/i915/reg: fix SKL scaler " Jani Nikula
2024-09-09 21:01 ` Ville Syrjälä
2024-09-09 18:58 ` [PATCH 06/11] drm/i915/reg: fix PCH transcoder timing and data/link m/n style Jani Nikula
2024-09-09 21:01 ` Ville Syrjälä
2024-09-10 8:05 ` Jani Nikula [this message]
2024-09-10 11:48 ` Ville Syrjälä
2024-09-09 18:58 ` [PATCH 07/11] drm/i915/reg: fix DIP CTL register style Jani Nikula
2024-09-09 18:58 ` [PATCH 08/11] drm/i915/reg: fix small register style issues here and there Jani Nikula
2024-09-09 18:59 ` [PATCH 09/11] drm/i915/reg: remove unused DSI register macros Jani Nikula
2024-09-09 18:59 ` [PATCH 10/11] drm/i915/reg: remove superfluous whitespace Jani Nikula
2024-09-09 18:59 ` [PATCH 11/11] drm/i915: split out display regs from i915_reg.h Jani Nikula
2024-09-09 20:57 ` Ville Syrjälä
2024-09-09 21:18 ` Jani Nikula
2024-09-10 11:58 ` Ville Syrjälä
2024-09-09 21:03 ` [PATCH 00/11] drm/i915: split out display regs Ville Syrjälä
2024-09-10 13:32 ` Jani Nikula
2024-09-09 21:10 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2024-09-09 21:10 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-09-09 21:19 ` ✓ Fi.CI.BAT: success " Patchwork
2024-09-10 23:20 ` ✗ Fi.CI.IGT: failure " Patchwork
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