Re: [Intel-gfx] [PATCH] drm/i915/display/dp: Change DSC vs lower bpp priority

[Jani Nikula <jani.nikula@linux.intel.com>]

On Wed, 20 Sep 2023, Charlton Lin <charlton.lin@intel.com> wrote:
> Previously driver would lower bpp before trying DSC. Monitors
> capable of acheiving highest mode with either DSC or lower bpp
> would have bpp dropped instead of attempting DSC at higher bpp.
>
> Changed the order in which driver attempts DSC and lower bpp.
> Attempt DSC before trying lower bpp without DSC.

It's not clear that the highest bpp with DSC is always the best
option. It may be in some cases, for some displays, but not always.

This is policy that really belongs in the userspace, but we have no
mechanism to give userspace the option.

As to the implementation, I think this frankly looks like a hack. Try
this and that, with various options, and try again. Not nice.

What I think we'll need (regardless of the patch at hand) is a way to
generate an ordered list of link parameters to try, which is also used
for link training failure fallback. The parameters should include lane
count, link rate, bpp, dsc, 128b/132b vs 8b/10b. For example, you might
want to first try 128b/132b without dsc, then 8b/10b with dsc, etc. Stop
trying to iterate in nested for loops, because they can't handle all
cases.

With that, it *might* be easier to provide a mechanism for userspace to
prefer some options.


BR,
Jani.



>
> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Cc: Suraj Kandpal <suraj.kandpal@intel.com>
> Cc: Khaled Almahallawy <khaled.almahallawy@intel.com>
> Signed-off-by: Charlton Lin <charlton.lin@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 19 ++++++++++++++-----
>  1 file changed, 14 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 2206b45bc78c..0d65ca4085b4 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1527,12 +1527,14 @@ static int
>  intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
>  				  struct intel_crtc_state *pipe_config,
>  				  const struct drm_connector_state *conn_state,
> -				  const struct link_config_limits *limits)
> +				  const struct link_config_limits *limits,
> +				  bool allow_bpp_change)
>  {
>  	int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state);
>  	int mode_rate, link_rate, link_avail;
> +	int min_bpp = allow_bpp_change ? limits->min_bpp : limits->max_bpp;
>  
> -	for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
> +	for (bpp = limits->max_bpp; bpp >= min_bpp; bpp -= 2 * 3) {
>  		int link_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
>  
>  		mode_rate = intel_dp_link_required(clock, link_bpp);
> @@ -2247,7 +2249,8 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
>  	 * Optimize for slow and wide for everything, because there are some
>  	 * eDP 1.3 and 1.4 panels don't work well with fast and narrow.
>  	 */
> -	ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, conn_state, &limits);
> +	ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config,
> +						conn_state, &limits, false);
>  
>  	if (ret || joiner_needs_dsc || intel_dp->force_dsc_en) {
>  		drm_dbg_kms(&i915->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n",
> @@ -2255,10 +2258,16 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
>  			    str_yes_no(intel_dp->force_dsc_en));
>  		ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
>  						  conn_state, &limits, 64, true);
> -		if (ret < 0)
> -			return ret;
>  	}
>  
> +	if (ret < 0)
> +		ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config,
> +							conn_state, &limits,
> +							true);
> +
> +	if (ret < 0)
> +		return ret;
> +
>  	if (pipe_config->dsc.compression_enable) {
>  		drm_dbg_kms(&i915->drm,
>  			    "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",

-- 
Jani Nikula, Intel