From: Jani Nikula <jani.nikula@intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH -fixes] drm/i915/display: Prevent double YUV range correction on HDR planes
Date: Tue, 02 Feb 2021 12:43:37 +0200 [thread overview]
Message-ID: <87czxihhra.fsf@intel.com> (raw)
In-Reply-To: <20210202084553.30691-1-ville.syrjala@linux.intel.com>
On Tue, 02 Feb 2021, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Andres Calderon Jaramillo <andrescj@chromium.org>
>
> Prevent the ICL HDR plane pipeline from performing YUV color range
> correction twice when the input is in limited range. This is done by
> removing the limited-range code from icl_program_input_csc().
>
> Before this patch the following could happen: user space gives us a YUV
> buffer in limited range; per the pipeline in [1], the plane would first
> go through a "YUV Range correct" stage that expands the range; the plane
> would then go through the "Input CSC" stage which would also expand the
> range because icl_program_input_csc() would use a matrix and an offset
> that assume limited-range input; this would ultimately cause dark and
> light colors to appear darker and lighter than they should respectively.
>
> This is an issue because if a buffer switches between being scanned out
> and being composited with the GPU, the user will see a color difference.
> If this switching happens quickly and frequently, the user will perceive
> this as a flickering.
>
> [1] https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc-icllp-vol12-displayengine_0.pdf#page=281
>
> Cc: stable@vger.kernel.org
> Signed-off-by: Andres Calderon Jaramillo <andrescj@chromium.org>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Link: https://patchwork.freedesktop.org/patch/msgid/20201215224219.3896256-1-andrescj@google.com
> (cherry picked from commit fed387572040e84ead53852a7820e30a30e515d0)
Thanks, pushed to drm-intel-fixes.
BR,
Jani.
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 2 +
> drivers/gpu/drm/i915/display/intel_sprite.c | 65 +++-----------------
> 2 files changed, 12 insertions(+), 55 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 53a00cf3fa32..39396248f388 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -4807,6 +4807,8 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
> plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
> } else if (fb->format->is_yuv) {
> plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
> + if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
> + plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
> }
>
> return plane_color_ctl;
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 019a2d6d807a..3da2544fa1c0 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -618,13 +618,19 @@ skl_program_scaler(struct intel_plane *plane,
>
> /* Preoffset values for YUV to RGB Conversion */
> #define PREOFF_YUV_TO_RGB_HI 0x1800
> -#define PREOFF_YUV_TO_RGB_ME 0x1F00
> +#define PREOFF_YUV_TO_RGB_ME 0x0000
> #define PREOFF_YUV_TO_RGB_LO 0x1800
>
> #define ROFF(x) (((x) & 0xffff) << 16)
> #define GOFF(x) (((x) & 0xffff) << 0)
> #define BOFF(x) (((x) & 0xffff) << 16)
>
> +/*
> + * Programs the input color space conversion stage for ICL HDR planes.
> + * Note that it is assumed that this stage always happens after YUV
> + * range correction. Thus, the input to this stage is assumed to be
> + * in full-range YCbCr.
> + */
> static void
> icl_program_input_csc(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state,
> @@ -672,52 +678,7 @@ icl_program_input_csc(struct intel_plane *plane,
> 0x0, 0x7800, 0x7F10,
> },
> };
> -
> - /* Matrix for Limited Range to Full Range Conversion */
> - static const u16 input_csc_matrix_lr[][9] = {
> - /*
> - * BT.601 Limted range YCbCr -> full range RGB
> - * The matrix required is :
> - * [1.164384, 0.000, 1.596027,
> - * 1.164384, -0.39175, -0.812813,
> - * 1.164384, 2.017232, 0.0000]
> - */
> - [DRM_COLOR_YCBCR_BT601] = {
> - 0x7CC8, 0x7950, 0x0,
> - 0x8D00, 0x7950, 0x9C88,
> - 0x0, 0x7950, 0x6810,
> - },
> - /*
> - * BT.709 Limited range YCbCr -> full range RGB
> - * The matrix required is :
> - * [1.164384, 0.000, 1.792741,
> - * 1.164384, -0.213249, -0.532909,
> - * 1.164384, 2.112402, 0.0000]
> - */
> - [DRM_COLOR_YCBCR_BT709] = {
> - 0x7E58, 0x7950, 0x0,
> - 0x8888, 0x7950, 0xADA8,
> - 0x0, 0x7950, 0x6870,
> - },
> - /*
> - * BT.2020 Limited range YCbCr -> full range RGB
> - * The matrix required is :
> - * [1.164, 0.000, 1.678,
> - * 1.164, -0.1873, -0.6504,
> - * 1.164, 2.1417, 0.0000]
> - */
> - [DRM_COLOR_YCBCR_BT2020] = {
> - 0x7D70, 0x7950, 0x0,
> - 0x8A68, 0x7950, 0xAC00,
> - 0x0, 0x7950, 0x6890,
> - },
> - };
> - const u16 *csc;
> -
> - if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
> - csc = input_csc_matrix[plane_state->hw.color_encoding];
> - else
> - csc = input_csc_matrix_lr[plane_state->hw.color_encoding];
> + const u16 *csc = input_csc_matrix[plane_state->hw.color_encoding];
>
> intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 0),
> ROFF(csc[0]) | GOFF(csc[1]));
> @@ -734,14 +695,8 @@ icl_program_input_csc(struct intel_plane *plane,
>
> intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 0),
> PREOFF_YUV_TO_RGB_HI);
> - if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
> - intel_de_write_fw(dev_priv,
> - PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1),
> - 0);
> - else
> - intel_de_write_fw(dev_priv,
> - PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1),
> - PREOFF_YUV_TO_RGB_ME);
> + intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1),
> + PREOFF_YUV_TO_RGB_ME);
> intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 2),
> PREOFF_YUV_TO_RGB_LO);
> intel_de_write_fw(dev_priv,
--
Jani Nikula, Intel Open Source Graphics Center
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Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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next prev parent reply other threads:[~2021-02-02 10:43 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-18 9:07 [Intel-gfx] Fixes that failed to apply to v5.11-rc4 Jani Nikula
2021-01-18 9:53 ` [Intel-gfx] [PATCH] drm/i915/gt: Prevent use of engine->wa_ctx after error Chris Wilson
2021-01-18 10:07 ` [Intel-gfx] [PATCH] drm/i915/pmu: Don't grab wakeref when enabling events Chris Wilson
2021-01-18 10:14 ` Tvrtko Ursulin
2021-01-18 10:17 ` [Intel-gfx] [PATCH] drm/i915: Check for rq->hwsp validity after acquiring RCU lock Chris Wilson
2021-01-18 12:35 ` Jani Nikula
2021-01-18 10:18 ` [Intel-gfx] Fixes that failed to apply to v5.11-rc4 Chris Wilson
2021-01-18 14:19 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Check for rq->hwsp validity after acquiring RCU lock (rev2) Patchwork
2021-01-18 15:43 ` [Intel-gfx] [PATCH -fixes] drm/i915: Only enable DFP 4:4:4->4:2:0 conversion when outputting YCbCr 4:4:4 Ville Syrjala
2021-01-19 8:50 ` Jani Nikula
2021-02-02 7:15 ` [Intel-gfx] Fixes that failed to apply to v5.11-rc4 Jani Nikula
2021-02-02 8:27 ` Chris Wilson
2021-02-02 11:52 ` Jani Nikula
2021-02-02 8:45 ` [Intel-gfx] [PATCH -fixes] drm/i915/display: Prevent double YUV range correction on HDR planes Ville Syrjala
2021-02-02 10:43 ` Jani Nikula [this message]
2021-02-02 8:50 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/display: Prevent double YUV range correction on HDR planes (rev3) Patchwork
2021-02-02 14:26 ` [Intel-gfx] Fixes that failed to apply to v5.11-rc4 Imre Deak
2021-02-02 15:47 ` Jani Nikula
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