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From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Subject: Re: [Intel-gfx] [PATCH] drm/i915/gt: Move gen8 CS emitters into gen8_engine_cs.h
Date: Wed, 16 Dec 2020 17:36:31 +0200	[thread overview]
Message-ID: <87eejpn4ow.fsf@gaia.fi.intel.com> (raw)
In-Reply-To: <20201216135452.6063-1-chris@chris-wilson.co.uk>

Chris Wilson <chris@chris-wilson.co.uk> writes:

> Reduce the pollution of intel_engine.h by moving gen8_emit_pipe_control
> and friends to gen8_engine_cs.h
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_overlay.c  |  1 +
>  drivers/gpu/drm/i915/gem/i915_gem_context.c   |  1 +
>  .../gpu/drm/i915/gem/i915_gem_execbuffer.c    |  1 +
>  .../gpu/drm/i915/gem/i915_gem_object_blt.c    |  1 +
>  .../i915/gem/selftests/i915_gem_coherency.c   |  1 +
>  .../drm/i915/gem/selftests/i915_gem_mman.c    |  1 +
>  .../drm/i915/gem/selftests/igt_gem_utils.c    |  1 +
>  drivers/gpu/drm/i915/gt/gen8_engine_cs.h      | 92 +++++++++++++++++++
>  drivers/gpu/drm/i915/gt/intel_engine.h        | 86 -----------------
>  drivers/gpu/drm/i915/gt/intel_renderstate.c   |  3 +-
>  drivers/gpu/drm/i915/gt/intel_ring.c          |  2 +
>  drivers/gpu/drm/i915/gt/intel_workarounds.c   |  1 +
>  drivers/gpu/drm/i915/gt/selftest_engine_cs.c  |  1 +
>  drivers/gpu/drm/i915/gt/selftest_engine_pm.c  |  2 +
>  drivers/gpu/drm/i915/gt/selftest_mocs.c       |  1 +
>  drivers/gpu/drm/i915/gt/selftest_rc6.c        |  1 +
>  drivers/gpu/drm/i915/gt/selftest_reset.c      |  1 +
>  drivers/gpu/drm/i915/gt/selftest_timeline.c   |  1 +
>  drivers/gpu/drm/i915/gvt/cmd_parser.c         |  1 +
>  drivers/gpu/drm/i915/gvt/mmio_context.c       |  1 +
>  drivers/gpu/drm/i915/i915_cmd_parser.c        |  1 +
>  drivers/gpu/drm/i915/i915_perf.c              |  1 +
>  drivers/gpu/drm/i915/i915_request.c           |  1 +
>  drivers/gpu/drm/i915/selftests/i915_gem_gtt.c |  1 +
>  drivers/gpu/drm/i915/selftests/igt_spinner.c  |  1 +
>  25 files changed, 118 insertions(+), 87 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c
> index 52b4f6193b4c..6be5d8946c69 100644
> --- a/drivers/gpu/drm/i915/display/intel_overlay.c
> +++ b/drivers/gpu/drm/i915/display/intel_overlay.c
> @@ -29,6 +29,7 @@
>  #include <drm/drm_fourcc.h>
>  
>  #include "gem/i915_gem_pm.h"
> +#include "gt/intel_gpu_commands.h"
>  #include "gt/intel_ring.h"
>  
>  #include "i915_drv.h"
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index ad136d009d9b..7aa4629f6111 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -73,6 +73,7 @@
>  #include "gt/intel_engine_heartbeat.h"
>  #include "gt/intel_engine_user.h"
>  #include "gt/intel_execlists_submission.h" /* virtual_engine */
> +#include "gt/intel_gpu_commands.h"
>  #include "gt/intel_ring.h"
>  
>  #include "i915_gem_context.h"
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> index 2ff32daa50bd..0cf9e79325a8 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> @@ -15,6 +15,7 @@
>  
>  #include "gem/i915_gem_ioctls.h"
>  #include "gt/intel_context.h"
> +#include "gt/intel_gpu_commands.h"
>  #include "gt/intel_gt.h"
>  #include "gt/intel_gt_buffer_pool.h"
>  #include "gt/intel_gt_pm.h"
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
> index aee7ad3cc3c6..10cac9fac79b 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
> @@ -6,6 +6,7 @@
>  #include "i915_drv.h"
>  #include "gt/intel_context.h"
>  #include "gt/intel_engine_pm.h"
> +#include "gt/intel_gpu_commands.h"
>  #include "gt/intel_gt.h"
>  #include "gt/intel_gt_buffer_pool.h"
>  #include "gt/intel_ring.h"
> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
> index 7049a6bbc03d..1117d2a44518 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
> @@ -7,6 +7,7 @@
>  #include <linux/prime_numbers.h>
>  
>  #include "gt/intel_engine_pm.h"
> +#include "gt/intel_gpu_commands.h"
>  #include "gt/intel_gt.h"
>  #include "gt/intel_gt_pm.h"
>  #include "gt/intel_ring.h"
> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> index d27d87a678c8..d429c7643ff2 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> @@ -7,6 +7,7 @@
>  #include <linux/prime_numbers.h>
>  
>  #include "gt/intel_engine_pm.h"
> +#include "gt/intel_gpu_commands.h"
>  #include "gt/intel_gt.h"
>  #include "gt/intel_gt_pm.h"
>  #include "gem/i915_gem_region.h"
> diff --git a/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c b/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c
> index e21b5023ca7d..d6783061bc72 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c
> @@ -9,6 +9,7 @@
>  #include "gem/i915_gem_context.h"
>  #include "gem/i915_gem_pm.h"
>  #include "gt/intel_context.h"
> +#include "gt/intel_gpu_commands.h"
>  #include "gt/intel_gt.h"
>  #include "i915_vma.h"
>  #include "i915_drv.h"
> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.h b/drivers/gpu/drm/i915/gt/gen8_engine_cs.h
> index 3c5771fea235..38142c0d6dde 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.h
> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.h
> @@ -6,8 +6,13 @@
>  #ifndef __GEN8_ENGINE_CS_H__
>  #define __GEN8_ENGINE_CS_H__
>  
> +#include <linux/string.h>
>  #include <linux/types.h>
>  
> +#include "i915_gem.h" /* GEM_BUG_ON */
> +
> +#include "intel_gpu_commands.h"
> +
>  struct i915_request;
>  
>  int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode);
> @@ -33,4 +38,91 @@ u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs);
>  u32 *gen11_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs);
>  u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs);
>  
> +
> +static inline u32 *
> +__gen8_emit_pipe_control(u32 *batch, u32 flags0, u32 flags1, u32 offset)
> +{
> +	memset(batch, 0, 6 * sizeof(u32));
> +
> +	batch[0] = GFX_OP_PIPE_CONTROL(6) | flags0;
> +	batch[1] = flags1;
> +	batch[2] = offset;
> +
> +	return batch + 6;
> +}
> +
> +static inline u32 *gen8_emit_pipe_control(u32 *batch, u32 flags, u32 offset)
> +{
> +	return __gen8_emit_pipe_control(batch, 0, flags, offset);
> +}
> +
> +static inline u32 *gen12_emit_pipe_control(u32 *batch, u32 flags0, u32 flags1, u32 offset)
> +{
> +	return __gen8_emit_pipe_control(batch, flags0, flags1, offset);
> +}
> +
> +static inline u32 *
> +__gen8_emit_write_rcs(u32 *cs, u32 value, u32 offset, u32 flags0, u32 flags1)
> +{
> +	*cs++ = GFX_OP_PIPE_CONTROL(6) | flags0;
> +	*cs++ = flags1 | PIPE_CONTROL_QW_WRITE;
> +	*cs++ = offset;
> +	*cs++ = 0;
> +	*cs++ = value;
> +	*cs++ = 0; /* We're thrashing one extra dword. */
> +
> +	return cs;
> +}
> +
> +static inline u32*
> +gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
> +{
> +	/* We're using qword write, offset should be aligned to 8 bytes. */
> +	GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
> +
> +	return __gen8_emit_write_rcs(cs,
> +				     value,
> +				     gtt_offset,
> +				     0,
> +				     flags | PIPE_CONTROL_GLOBAL_GTT_IVB);
> +}
> +
> +static inline u32*
> +gen12_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags0, u32 flags1)
> +{
> +	/* We're using qword write, offset should be aligned to 8 bytes. */
> +	GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
> +
> +	return __gen8_emit_write_rcs(cs,
> +				     value,
> +				     gtt_offset,
> +				     flags0,
> +				     flags1 | PIPE_CONTROL_GLOBAL_GTT_IVB);
> +}
> +
> +static inline u32 *
> +__gen8_emit_flush_dw(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
> +{
> +	*cs++ = (MI_FLUSH_DW + 1) | flags;
> +	*cs++ = gtt_offset;
> +	*cs++ = 0;
> +	*cs++ = value;
> +
> +	return cs;
> +}
> +
> +static inline u32 *
> +gen8_emit_ggtt_write(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
> +{
> +	/* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
> +	GEM_BUG_ON(gtt_offset & (1 << 5));
> +	/* Offset should be aligned to 8 bytes for both (QW/DW) write types */
> +	GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
> +
> +	return __gen8_emit_flush_dw(cs,
> +				    value,
> +				    gtt_offset | MI_FLUSH_DW_USE_GTT,
> +				    flags | MI_FLUSH_DW_OP_STOREDW);
> +}
> +
>  #endif /* __GEN8_ENGINE_CS_H__ */
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
> index 760fefdfe392..6606b1dbf3d6 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine.h
> @@ -15,7 +15,6 @@
>  #include "i915_selftest.h"
>  #include "gt/intel_timeline.h"
>  #include "intel_engine_types.h"
> -#include "intel_gpu_commands.h"
>  #include "intel_workarounds.h"
>  
>  struct drm_printer;
> @@ -223,91 +222,6 @@ void intel_engine_get_instdone(const struct intel_engine_cs *engine,
>  
>  void intel_engine_init_execlists(struct intel_engine_cs *engine);
>  
> -static inline u32 *__gen8_emit_pipe_control(u32 *batch, u32 flags0, u32 flags1, u32 offset)
> -{
> -	memset(batch, 0, 6 * sizeof(u32));
> -
> -	batch[0] = GFX_OP_PIPE_CONTROL(6) | flags0;
> -	batch[1] = flags1;
> -	batch[2] = offset;
> -
> -	return batch + 6;
> -}
> -
> -static inline u32 *gen8_emit_pipe_control(u32 *batch, u32 flags, u32 offset)
> -{
> -	return __gen8_emit_pipe_control(batch, 0, flags, offset);
> -}
> -
> -static inline u32 *gen12_emit_pipe_control(u32 *batch, u32 flags0, u32 flags1, u32 offset)
> -{
> -	return __gen8_emit_pipe_control(batch, flags0, flags1, offset);
> -}
> -
> -static inline u32 *
> -__gen8_emit_write_rcs(u32 *cs, u32 value, u32 offset, u32 flags0, u32 flags1)
> -{
> -	*cs++ = GFX_OP_PIPE_CONTROL(6) | flags0;
> -	*cs++ = flags1 | PIPE_CONTROL_QW_WRITE;
> -	*cs++ = offset;
> -	*cs++ = 0;
> -	*cs++ = value;
> -	*cs++ = 0; /* We're thrashing one extra dword. */
> -
> -	return cs;
> -}
> -
> -static inline u32*
> -gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
> -{
> -	/* We're using qword write, offset should be aligned to 8 bytes. */
> -	GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
> -
> -	return __gen8_emit_write_rcs(cs,
> -				     value,
> -				     gtt_offset,
> -				     0,
> -				     flags | PIPE_CONTROL_GLOBAL_GTT_IVB);
> -}
> -
> -static inline u32*
> -gen12_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags0, u32 flags1)
> -{
> -	/* We're using qword write, offset should be aligned to 8 bytes. */
> -	GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
> -
> -	return __gen8_emit_write_rcs(cs,
> -				     value,
> -				     gtt_offset,
> -				     flags0,
> -				     flags1 | PIPE_CONTROL_GLOBAL_GTT_IVB);
> -}
> -
> -static inline u32 *
> -__gen8_emit_flush_dw(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
> -{
> -	*cs++ = (MI_FLUSH_DW + 1) | flags;
> -	*cs++ = gtt_offset;
> -	*cs++ = 0;
> -	*cs++ = value;
> -
> -	return cs;
> -}
> -
> -static inline u32 *
> -gen8_emit_ggtt_write(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
> -{
> -	/* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
> -	GEM_BUG_ON(gtt_offset & (1 << 5));
> -	/* Offset should be aligned to 8 bytes for both (QW/DW) write types */
> -	GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
> -
> -	return __gen8_emit_flush_dw(cs,
> -				    value,
> -				    gtt_offset | MI_FLUSH_DW_USE_GTT,
> -				    flags | MI_FLUSH_DW_OP_STOREDW);
> -}
> -
>  static inline void __intel_engine_reset(struct intel_engine_cs *engine,
>  					bool stalled)
>  {
> diff --git a/drivers/gpu/drm/i915/gt/intel_renderstate.c b/drivers/gpu/drm/i915/gt/intel_renderstate.c
> index ea2a77c7b469..ca816ba22197 100644
> --- a/drivers/gpu/drm/i915/gt/intel_renderstate.c
> +++ b/drivers/gpu/drm/i915/gt/intel_renderstate.c
> @@ -27,7 +27,8 @@
>  
>  #include "i915_drv.h"
>  #include "intel_renderstate.h"
> -#include "gt/intel_context.h"
> +#include "intel_context.h"
> +#include "intel_gpu_commands.h"
>  #include "intel_ring.h"
>  
>  static const struct intel_renderstate_rodata *
> diff --git a/drivers/gpu/drm/i915/gt/intel_ring.c b/drivers/gpu/drm/i915/gt/intel_ring.c
> index 4034a4bac7f0..06385550450c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ring.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ring.c
> @@ -5,9 +5,11 @@
>   */
>  
>  #include "gem/i915_gem_object.h"
> +
>  #include "i915_drv.h"
>  #include "i915_vma.h"
>  #include "intel_engine.h"
> +#include "intel_gpu_commands.h"
>  #include "intel_ring.h"
>  #include "intel_timeline.h"
>  
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 52f12a6d66b9..38868c5c038e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -7,6 +7,7 @@
>  #include "i915_drv.h"
>  #include "intel_context.h"
>  #include "intel_engine_pm.h"
> +#include "intel_gpu_commands.h"
>  #include "intel_gt.h"
>  #include "intel_ring.h"
>  #include "intel_workarounds.h"
> diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
> index 729c3c7b11e2..439c8984f5fa 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
> @@ -6,6 +6,7 @@
>  
>  #include <linux/sort.h>
>  
> +#include "intel_gpu_commands.h"
>  #include "intel_gt_pm.h"
>  #include "intel_rps.h"
>  
> diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
> index b08fc5390e8a..163a10b07f85 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
> @@ -4,6 +4,8 @@
>   * Copyright © 2018 Intel Corporation
>   */
>  
> +#include "intel_gpu_commands.h"
> +
>  #include "i915_selftest.h"
>  #include "selftest_engine.h"
>  #include "selftest_engine_heartbeat.h"
> diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c b/drivers/gpu/drm/i915/gt/selftest_mocs.c
> index 21dcd91cbd62..37b066dca52c 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c
> @@ -5,6 +5,7 @@
>   */
>  
>  #include "gt/intel_engine_pm.h"
> +#include "gt/intel_gpu_commands.h"
>  #include "i915_selftest.h"
>  
>  #include "gem/selftests/mock_context.h"
> diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c b/drivers/gpu/drm/i915/gt/selftest_rc6.c
> index 64ef5ee5decf..61abc0556601 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_rc6.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c
> @@ -6,6 +6,7 @@
>  
>  #include "intel_context.h"
>  #include "intel_engine_pm.h"
> +#include "intel_gpu_commands.h"
>  #include "intel_gt_requests.h"
>  #include "intel_ring.h"
>  #include "selftest_rc6.h"
> diff --git a/drivers/gpu/drm/i915/gt/selftest_reset.c b/drivers/gpu/drm/i915/gt/selftest_reset.c
> index ef5aeebbeeb0..e4645c8bb00a 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_reset.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_reset.c
> @@ -9,6 +9,7 @@
>  
>  #include "i915_memcpy.h"
>  #include "i915_selftest.h"
> +#include "intel_gpu_commands.h"
>  #include "selftests/igt_reset.h"
>  #include "selftests/igt_atomic.h"
>  #include "selftests/igt_spinner.h"
> diff --git a/drivers/gpu/drm/i915/gt/selftest_timeline.c b/drivers/gpu/drm/i915/gt/selftest_timeline.c
> index e4285d5a0360..6f3a3687ef0f 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_timeline.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c
> @@ -9,6 +9,7 @@
>  #include "intel_context.h"
>  #include "intel_engine_heartbeat.h"
>  #include "intel_engine_pm.h"
> +#include "intel_gpu_commands.h"
>  #include "intel_gt.h"
>  #include "intel_gt_requests.h"
>  #include "intel_ring.h"
> diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
> index 16b582cb97ed..3fea967ee817 100644
> --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
> +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
> @@ -37,6 +37,7 @@
>  #include <linux/slab.h>
>  
>  #include "i915_drv.h"
> +#include "gt/intel_gpu_commands.h"
>  #include "gt/intel_ring.h"
>  #include "gvt.h"
>  #include "i915_pvinfo.h"
> diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
> index afe574d6b3b5..c9589e26af93 100644
> --- a/drivers/gpu/drm/i915/gvt/mmio_context.c
> +++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
> @@ -35,6 +35,7 @@
>  
>  #include "i915_drv.h"
>  #include "gt/intel_context.h"
> +#include "gt/intel_gpu_commands.h"
>  #include "gt/intel_ring.h"
>  #include "gvt.h"
>  #include "trace.h"
> diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> index 93265951fdbb..8d88402387bd 100644
> --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> @@ -26,6 +26,7 @@
>   */
>  
>  #include "gt/intel_engine.h"
> +#include "gt/intel_gpu_commands.h"
>  
>  #include "i915_drv.h"
>  #include "i915_memcpy.h"
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index f553caf4b06d..58caa3f1a38b 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -199,6 +199,7 @@
>  #include "gt/intel_engine_pm.h"
>  #include "gt/intel_engine_user.h"
>  #include "gt/intel_execlists_submission.h"
> +#include "gt/intel_gpu_commands.h"
>  #include "gt/intel_gt.h"
>  #include "gt/intel_lrc_reg.h"
>  #include "gt/intel_ring.h"
> diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
> index a9db1376b996..2675c6d70779 100644
> --- a/drivers/gpu/drm/i915/i915_request.c
> +++ b/drivers/gpu/drm/i915/i915_request.c
> @@ -33,6 +33,7 @@
>  #include "gem/i915_gem_context.h"
>  #include "gt/intel_breadcrumbs.h"
>  #include "gt/intel_context.h"
> +#include "gt/intel_gpu_commands.h"
>  #include "gt/intel_ring.h"
>  #include "gt/intel_rps.h"
>  
> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
> index c53a222e3dec..70e07e9b78c2 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
> @@ -28,6 +28,7 @@
>  #include "gem/i915_gem_context.h"
>  #include "gem/selftests/mock_context.h"
>  #include "gt/intel_context.h"
> +#include "gt/intel_gpu_commands.h"
>  
>  #include "i915_random.h"
>  #include "i915_selftest.h"
> diff --git a/drivers/gpu/drm/i915/selftests/igt_spinner.c b/drivers/gpu/drm/i915/selftests/igt_spinner.c
> index ec0ecb4e4ca6..1216d919185e 100644
> --- a/drivers/gpu/drm/i915/selftests/igt_spinner.c
> +++ b/drivers/gpu/drm/i915/selftests/igt_spinner.c
> @@ -3,6 +3,7 @@
>   *
>   * Copyright © 2018 Intel Corporation
>   */
> +#include "gt/intel_gpu_commands.h"
>  #include "gt/intel_gt.h"
>  
>  #include "gem/selftests/igt_gem_utils.h"
> -- 
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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  parent reply	other threads:[~2020-12-16 15:38 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-16 13:54 [Intel-gfx] [PATCH] drm/i915/gt: Move gen8 CS emitters into gen8_engine_cs.h Chris Wilson
2020-12-16 14:09 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2020-12-16 14:38 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-12-16 15:36 ` Mika Kuoppala [this message]
2020-12-16 17:34 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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