Re: [Intel-gfx] [PATCH 1/4] drm/i915/panelreplay: dpcd register definition for panelreplay

[Jani Nikula <jani.nikula@linux.intel.com>]

On Thu, 10 Nov 2022, Animesh Manna <animesh.manna@intel.com> wrote:
> DPCD register definition added to check and enable panel replay
> capability of the sink.

This patch is not i915 specific like the subject claims.

Please always Cc: dri-devel for drm changes.

BR,
Jani.

>
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  include/drm/display/drm_dp.h | 11 +++++++++++
>  1 file changed, 11 insertions(+)
>
> diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
> index e934aab357be..40995f8c2c2f 100644
> --- a/include/drm/display/drm_dp.h
> +++ b/include/drm/display/drm_dp.h
> @@ -537,6 +537,10 @@
>  /* DFP Capability Extension */
>  #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT	0x0a3	/* 2.0 */
>  
> +#define DP_PANEL_REPLAY_CAP                 0x0b0
> +# define DP_PANEL_REPLAY_SUPPORT            (1 << 0)
> +# define DP_PR_SELECTIVE_UPDATE_SUPPORT     (1 << 1)
> +
>  /* Link Configuration */
>  #define	DP_LINK_BW_SET		            0x100
>  # define DP_LINK_RATE_TABLE		    0x00    /* eDP 1.4 */
> @@ -706,6 +710,13 @@
>  #define DP_BRANCH_DEVICE_CTRL		    0x1a1
>  # define DP_BRANCH_DEVICE_IRQ_HPD	    (1 << 0)
>  
> +#define PANEL_REPLAY_CONFIG                 0x1b0
> +# define DP_PANEL_REPLAY_ENABLE             (1 << 0)
> +# define DP_PR_UNRECOVERABLE_ERROR          (1 << 3)
> +# define DP_PR_RFB_STORAGE_ERROR            (1 << 4)
> +# define DP_PR_ACTIVE_FRAME_CRC_ERROR       (1 << 5)
> +# define DP_PR_SELECTIVE_UPDATE_ENABLE      (1 << 6)
> +
>  #define DP_PAYLOAD_ALLOCATE_SET		    0x1c0
>  #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
>  #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2

-- 
Jani Nikula, Intel Open Source Graphics Center