Re: [Intel-gfx] [PATCH v3 13/13] drm/i915/dsi: add support for DSC

[Jani Nikula <jani.nikula@intel.com>]

On Thu, 05 Dec 2019, "Kulkarni, Vandita" <vandita.kulkarni@intel.com> wrote:
>> -----Original Message-----
>> From: Jani Nikula <jani.nikula@intel.com>
>> Sent: Tuesday, November 26, 2019 7:13 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Nikula, Jani <jani.nikula@intel.com>; Kulkarni, Vandita
>> <vandita.kulkarni@intel.com>; Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Subject: [PATCH v3 13/13] drm/i915/dsi: add support for DSC
>> 
>> Enable DSC for DSI, if specified in VBT.
>> 
>> This still lacks DSC aware get config implementation, and therefore state
>> checker will fail. Also mode valid is not there yet.
>> 
>> v4:
>> - convert_rgb = true (Vandita)
>> - ignore max cdclock check (Vandita)
>> - rename pipe_config to crtc_state
>> 
>> v3:
>> - take compressed bpp into account
>> 
>> v2:
>> - Nuke conn_state->max_requested_bpc, it's not used on DSI
>> 
>> Bspec: 49263
>> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/icl_dsi.c | 67 ++++++++++++++++++++++++--
>>  1 file changed, 64 insertions(+), 3 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
>> b/drivers/gpu/drm/i915/display/icl_dsi.c
>> index caa477c4b1af..e142ac64f680 100644
>> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
>> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
>> @@ -34,6 +34,7 @@
>>  #include "intel_ddi.h"
>>  #include "intel_dsi.h"
>>  #include "intel_panel.h"
>> +#include "intel_vdsc.h"
>> 
>>  static inline int header_credits_available(struct drm_i915_private *dev_priv,
>>  					   enum transcoder dsi_trans)
>> @@ -1087,6 +1088,8 @@ static void gen11_dsi_pre_enable(struct
>> intel_encoder *encoder,
>>  	/* step5: program and powerup panel */
>>  	gen11_dsi_powerup_panel(encoder);
>> 
>> +	intel_dsc_enable(encoder, pipe_config);
>> +
>>  	/* step6c: configure transcoder timings */
>>  	gen11_dsi_set_transcoder_timings(encoder, pipe_config);
>> 
>> @@ -1248,6 +1251,13 @@ static void gen11_dsi_disable(struct
>> intel_encoder *encoder,
>>  	gen11_dsi_disable_io_power(encoder);
>>  }
>> 
>> +static enum drm_mode_status gen11_dsi_mode_valid(struct
>> drm_connector *connector,
>> +						 struct drm_display_mode
>> *mode)
>> +{
>> +	/* FIXME: DSC? */
>> +	return intel_dsi_mode_valid(connector, mode); }
>> +
>>  static void gen11_dsi_get_timings(struct intel_encoder *encoder,
>>  				  struct intel_crtc_state *pipe_config)  { @@ -
>> 1295,6 +1305,48 @@ static void gen11_dsi_get_config(struct intel_encoder
>> *encoder,
>>  	pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc);  }
>> 
>> +static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
>> +					struct intel_crtc_state *crtc_state) {
>> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>> +	struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
>> +	int dsc_max_bpc = INTEL_GEN(dev_priv) >= 12 ? 12 : 10;
>> +	bool use_dsc;
>> +	int ret;
>> +
>> +	use_dsc = intel_bios_get_dsc_params(encoder, crtc_state,
>> dsc_max_bpc);
>> +	if (!use_dsc)
>> +		return 0;
>> +
>> +	if (crtc_state->pipe_bpp < 8 * 3)
>> +		return -EINVAL;
>> +
>> +	/* FIXME: split only when necessary */
>> +	if (crtc_state->dsc.slice_count > 1)
>> +		crtc_state->dsc.dsc_split = true;
>> +
>> +	vdsc_cfg->convert_rgb = true;
>> +
>
> Is there a chance this might fail and pipe_config->bpp might remain
> changed as per what happens in intel_bios_get_dsc_params?

In theory, yes, but I'm doubtful we'll be able to get anything on screen
if VBT says DSC is required and it fails somehow.

BR,
Jani.

>
>> +	ret = intel_dsc_compute_params(encoder, crtc_state);
>> +	if (ret)
>> +		return ret;
>> +
>> +	/* DSI specific sanity checks on the common code */
>> +	WARN_ON(vdsc_cfg->vbr_enable);
>> +	WARN_ON(vdsc_cfg->simple_422);
>> +	WARN_ON(vdsc_cfg->pic_width % vdsc_cfg->slice_width);
>> +	WARN_ON(vdsc_cfg->slice_height < 8);
>> +	WARN_ON(vdsc_cfg->pic_height % vdsc_cfg->slice_height);
>> +
>> +	ret = drm_dsc_compute_rc_parameters(vdsc_cfg);
>> +	if (ret)
>> +		return ret;
>> +
>> +	crtc_state->dsc.compression_enable = true;
>> +
>> +	return 0;
>> +}
>> +
>>  static int gen11_dsi_compute_config(struct intel_encoder *encoder,
>>  				    struct intel_crtc_state *pipe_config,
>>  				    struct drm_connector_state *conn_state)
>> @@ -1326,6 +1378,10 @@ static int gen11_dsi_compute_config(struct
>> intel_encoder *encoder,
>>  		pipe_config->pipe_bpp = 18;
>> 
>>  	pipe_config->clock_set = true;
>> +
>> +	if (gen11_dsi_dsc_compute_config(encoder, pipe_config))
>> +		DRM_DEBUG_KMS("Attempting to use DSC failed\n");
>> +
>>  	pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5;
>> 
>>  	return 0;
>> @@ -1334,8 +1390,13 @@ static int gen11_dsi_compute_config(struct
>> intel_encoder *encoder,  static void gen11_dsi_get_power_domains(struct
>> intel_encoder *encoder,
>>  					struct intel_crtc_state *crtc_state)  {
>> -	get_dsi_io_power_domains(to_i915(encoder->base.dev),
>> -				 enc_to_intel_dsi(&encoder->base));
>> +	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>> +
>> +	get_dsi_io_power_domains(i915, enc_to_intel_dsi(&encoder-
>> >base));
>> +
>> +	if (crtc_state->dsc.compression_enable)
>> +		intel_display_power_get(i915,
>> +
>> 	intel_dsc_power_domain(crtc_state));
>>  }
>> 
>>  static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder, @@ -
>> 1405,7 +1466,7 @@ static const struct drm_connector_funcs
>> gen11_dsi_connector_funcs = {
>> 
>>  static const struct drm_connector_helper_funcs
>> gen11_dsi_connector_helper_funcs = {
>>  	.get_modes = intel_dsi_get_modes,
>> -	.mode_valid = intel_dsi_mode_valid,
>> +	.mode_valid = gen11_dsi_mode_valid,
>>  	.atomic_check = intel_digital_connector_atomic_check,
>>  };
>> 
>> --
>> 2.20.1
>

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx