From: Jani Nikula <jani.nikula@linux.intel.com>
To: Imre Deak <imre.deak@intel.com>,
intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org,
dri-devel@lists.freedesktop.org
Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Subject: Re: [PATCH] drm: Fix DSC BPP increment decoding
Date: Wed, 12 Feb 2025 18:46:40 +0200 [thread overview]
Message-ID: <87h64zyutr.fsf@intel.com> (raw)
In-Reply-To: <20250212161851.4007005-1-imre.deak@intel.com>
On Wed, 12 Feb 2025, Imre Deak <imre.deak@intel.com> wrote:
> Starting with DPCD version 2.0 bits 6:3 of the DP_DSC_BITS_PER_PIXEL_INC
> DPCD register contains the NativeYCbCr422_MAX_bpp_DELTA field, which can
> be non-zero as opposed to earlier DPCD versions, hence decoding the
> bit_per_pixel increment value at bits 2:0 in the same register requires
> applying a mask, do so.
>
> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Fixes: 0c2287c96521 ("drm/display/dp: Add helper function to get DSC bpp precision")
> Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
But we should really clean up the macros:
#define DP_DSC_BITS_PER_PIXEL_INC 0x06F
# define DP_DSC_RGB_YCbCr444_MAX_BPP_DELTA_MASK 0x1f
# define DP_DSC_RGB_YCbCr420_MAX_BPP_DELTA_MASK 0xe0
These are both for DPCD 0x6e, not 0x6f. They're misleading here. And
they should contain the /* DP 2.0 */ comment.
And a similar macro for 0x6f bits 6:3 could be added.
BR,
Jani.
> ---
> drivers/gpu/drm/display/drm_dp_helper.c | 2 +-
> include/drm/display/drm_dp.h | 1 +
> 2 files changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
> index c488d160a3c1f..f5c596234729d 100644
> --- a/drivers/gpu/drm/display/drm_dp_helper.c
> +++ b/drivers/gpu/drm/display/drm_dp_helper.c
> @@ -2602,7 +2602,7 @@ u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
> {
> u8 bpp_increment_dpcd = dsc_dpcd[DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT];
>
> - switch (bpp_increment_dpcd) {
> + switch (bpp_increment_dpcd & DP_DSC_BITS_PER_PIXEL_MASK) {
> case DP_DSC_BITS_PER_PIXEL_1_16:
> return 16;
> case DP_DSC_BITS_PER_PIXEL_1_8:
> diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
> index 784a32bfbad8f..c413ef68f9a30 100644
> --- a/include/drm/display/drm_dp.h
> +++ b/include/drm/display/drm_dp.h
> @@ -359,6 +359,7 @@
> # define DP_DSC_BITS_PER_PIXEL_1_4 0x2
> # define DP_DSC_BITS_PER_PIXEL_1_2 0x3
> # define DP_DSC_BITS_PER_PIXEL_1_1 0x4
> +# define DP_DSC_BITS_PER_PIXEL_MASK 0x7
>
> #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */
> # define DP_PSR_IS_SUPPORTED 1
--
Jani Nikula, Intel
next prev parent reply other threads:[~2025-02-12 16:46 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-12 16:18 [PATCH] drm: Fix DSC BPP increment decoding Imre Deak
2025-02-12 16:46 ` Jani Nikula [this message]
2025-02-13 8:33 ` Imre Deak
2025-02-12 19:49 ` ✗ Fi.CI.SPARSE: warning for " Patchwork
2025-02-12 20:04 ` ✓ i915.CI.BAT: success " Patchwork
2025-02-13 4:29 ` ✗ i915.CI.Full: failure " Patchwork
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