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From: Jani Nikula <jani.nikula@linux.intel.com>
To: Ankit Nautiyal <ankit.k.nautiyal@intel.com>,
	intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 1/5] drm/i915/dp: Add helper to check DSC1.2 for HDMI2.1 DFP
Date: Tue, 23 Aug 2022 14:02:06 +0300	[thread overview]
Message-ID: <87h723kytt.fsf@intel.com> (raw)
In-Reply-To: <20220822105426.3521960-2-ankit.k.nautiyal@intel.com>

On Mon, 22 Aug 2022, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
> Add helper function to check if Downstream HDMI 2.1 sink supports
> DSC1.2.

If we do this, are we going to add helpers for all the details in
display_info, when there's no conversions being done? I think the answer
should be "no".

i.e. why do we really need this?

BR,
Jani.

>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 13 +++++++++++--
>  1 file changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 32292c0be2bd..fdf82373a22d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -118,6 +118,15 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
>  static void intel_dp_unset_edid(struct intel_dp *intel_dp);
>  static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
>  
> +static bool
> +is_dfp_hdmi_sink_dsc_1_2(struct intel_dp *intel_dp)
> +{
> +	struct intel_connector *intel_connector = intel_dp->attached_connector;
> +	struct drm_connector *connector = &intel_connector->base;
> +
> +	return connector->display_info.hdmi.dsc_cap.v_1p2;
> +}
> +
>  /* Is link rate UHBR and thus 128b/132b? */
>  bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
>  {
> @@ -2393,7 +2402,7 @@ static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
>  	rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane;
>  	max_frl_rate = max_lanes * rate_per_lane;
>  
> -	if (connector->display_info.hdmi.dsc_cap.v_1p2) {
> +	if (is_dfp_hdmi_sink_dsc_1_2(intel_dp)) {
>  		max_dsc_lanes = connector->display_info.hdmi.dsc_cap.max_lanes;
>  		dsc_rate_per_lane = connector->display_info.hdmi.dsc_cap.max_frl_rate_per_lane;
>  		if (max_dsc_lanes && dsc_rate_per_lane)
> @@ -2605,7 +2614,7 @@ intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
>  	if (!intel_connector)
>  		return;
>  	connector = &intel_connector->base;
> -	hdmi_is_dsc_1_2 = connector->display_info.hdmi.dsc_cap.v_1p2;
> +	hdmi_is_dsc_1_2 = is_dfp_hdmi_sink_dsc_1_2(intel_dp);
>  
>  	if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) ||
>  	    !hdmi_is_dsc_1_2)

-- 
Jani Nikula, Intel Open Source Graphics Center

  reply	other threads:[~2022-08-23 11:02 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-22 10:54 [Intel-gfx] [PATCH 0/5] Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes Ankit Nautiyal
2022-08-22 10:54 ` [Intel-gfx] [PATCH 1/5] drm/i915/dp: Add helper to check DSC1.2 for HDMI2.1 DFP Ankit Nautiyal
2022-08-23 11:02   ` Jani Nikula [this message]
2022-08-24  7:46     ` Nautiyal, Ankit K
2022-08-22 10:54 ` [Intel-gfx] [PATCH 2/5] drm/i915/dp: Reset frl trained flag before restarting FRL training Ankit Nautiyal
2022-08-22 10:54 ` [Intel-gfx] [PATCH 3/5] drm/i915/dp: Fix DFP RGB->YCBCR conversion Ankit Nautiyal
2022-08-23 11:03   ` Jani Nikula
2022-08-24  7:58     ` Nautiyal, Ankit K
2022-08-24  8:37       ` Jani Nikula
2022-08-24 10:21         ` Nautiyal, Ankit K
2022-08-22 10:54 ` [Intel-gfx] [PATCH 4/5] drm/i915/dp: Handle BPP where HDMI2.1 DFP doesn't support DSC Ankit Nautiyal
2022-08-22 10:54 ` [Intel-gfx] [PATCH 5/5] drm/i915/dp: Fix FRL BW check for HDMI2.1 DFP Ankit Nautiyal
2022-08-22 13:17 ` [Intel-gfx] ✓ Fi.CI.BAT: success for Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes Patchwork
2022-08-23  0:19 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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