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From: Jani Nikula <jani.nikula@intel.com>
To: Animesh Manna <animesh.manna@intel.com>, intel-gfx@lists.freedesktop.org
Cc: gwan-gyeong.mun@intel.com, mika.kahola@intel.com,
	manasi.d.navare@intel.com, jose.souza@intel.com,
	Animesh Manna <animesh.manna@intel.com>
Subject: Re: [Intel-gfx] [PATCH v2 4/4] drm/i915/panelreplay: Added state checker for panel replay state
Date: Thu, 07 Oct 2021 20:52:05 +0300	[thread overview]
Message-ID: <87ily8yb7e.fsf@intel.com> (raw)
In-Reply-To: <20211007155729.27812-5-animesh.manna@intel.com>

On Thu, 07 Oct 2021, Animesh Manna <animesh.manna@intel.com> wrote:
> has_panel_replay flag is used to check panel replay state
> which is part of crtc_state structure.
>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 1 +
>  drivers/gpu/drm/i915/display/intel_psr.c     | 2 ++
>  2 files changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 4f0badb11bbb..a30b6fe87dfc 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -8136,6 +8136,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  			PIPE_CONF_CHECK_BOOL(has_psr);
>  			PIPE_CONF_CHECK_BOOL(has_psr2);
>  			PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
> +			PIPE_CONF_CHECK_BOOL(has_panel_replay);
>  			PIPE_CONF_CHECK_I(dc3co_exitline);
>  		}
>  	}
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 197cab7551c6..756f3c775e71 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1050,6 +1050,8 @@ void intel_psr_get_config(struct intel_encoder *encoder,
>  	 */
>  	pipe_config->has_psr = true;
>  	pipe_config->has_psr2 = intel_dp->psr.psr2_enabled;
> +	pipe_config->has_panel_replay = intel_dp->psr.enabled &&
> +					intel_dp_is_edp(intel_dp);

Get config is supposed to read the config from hardware, and then the
state checker compares sw and hw states. This seems off.

BR,
Jani.

>  	pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
>  
>  	if (!intel_dp->psr.psr2_enabled)

-- 
Jani Nikula, Intel Open Source Graphics Center

  reply	other threads:[~2021-10-07 17:52 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-07 15:57 [Intel-gfx] [PATCH v2 0/4] Panel replay phase1 implementation Animesh Manna
2021-10-07 15:57 ` [Intel-gfx] [PATCH v2 1/4] drm/i915/panelreplay: HAS_PR() macro added for panel replay Animesh Manna
2021-10-07 16:39   ` Ville Syrjälä
2021-10-07 16:56     ` Manna, Animesh
2021-10-07 16:59     ` Jani Nikula
2021-10-07 15:57 ` [Intel-gfx] [PATCH v2 2/4] drm/i915/panelreplay: Initializaton and compute config " Animesh Manna
2021-10-07 17:41   ` Jani Nikula
2021-10-08  9:18     ` Manna, Animesh
2021-10-07 17:41   ` Jani Nikula
2021-10-07 15:57 ` [Intel-gfx] [PATCH v2 3/4] drm/i915/panelreplay: enable/disable " Animesh Manna
2021-10-07 17:44   ` Jani Nikula
2021-10-07 15:57 ` [Intel-gfx] [PATCH v2 4/4] drm/i915/panelreplay: Added state checker for panel replay state Animesh Manna
2021-10-07 17:52   ` Jani Nikula [this message]
2021-10-07 16:47 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Panel replay phase1 implementation (rev2) Patchwork
2021-10-07 17:13 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork

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