From: Jani Nikula <jani.nikula@linux.intel.com>
To: "Surendrakumar Upadhyay\,
TejaskumarX" <tejaskumarx.surendrakumar.upadhyay@intel.com>,
"Souza\, Jose" <jose.souza@intel.com>,
"intel-gfx\@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH v2] drm/i915/display/ehl: Limit eDP to HBR2
Date: Thu, 01 Oct 2020 14:56:05 +0300 [thread overview]
Message-ID: <87k0wama7e.fsf@intel.com> (raw)
In-Reply-To: <SN6PR11MB34217BC5C5AE290B12C8123CDF330@SN6PR11MB3421.namprd11.prod.outlook.com>
On Wed, 30 Sep 2020, "Surendrakumar Upadhyay, TejaskumarX" <tejaskumarx.surendrakumar.upadhyay@intel.com> wrote:
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of José Roberto de Souza
> Sent: 29 September 2020 01:33
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v2] drm/i915/display/ehl: Limit eDP to HBR2
>
> Recent update in documentation defeatured eDP HBR3 for EHL and JSL.
>
> v2:
> - Remove dead code in ehl_get_combo_buf_trans()
>
> BSpec: 32247
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Vidya Srinivas <vidya.srinivas@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 9 ++------- drivers/gpu/drm/i915/display/intel_dp.c | 11 ++++++++++-
> 2 files changed, 12 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 4d06178cd76c..ef06b7b82be9 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1082,13 +1082,8 @@ ehl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
> return icl_combo_phy_ddi_translations_hdmi;
> case INTEL_OUTPUT_EDP:
> if (dev_priv->vbt.edp.low_vswing) {
> - if (rate > 540000) {
> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
> - return icl_combo_phy_ddi_translations_edp_hbr3;
> - } else {
> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
> - return icl_combo_phy_ddi_translations_edp_hbr2;
> - }
> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
> + return icl_combo_phy_ddi_translations_edp_hbr2;
>
> As pe Bspec, ehl_edp_hbr2 does not match with icl_edp_hbr2 values. Rather I see (icl_edp_hbr2 == ehl_edp_hbr) true.
>
> Thanks,
> Tejas
Tejas, please fix your email quoting when interacting on the public
lists. Using Outlook defaults is not acceptable. Please use settings to
prepend "> " to all lines of the email being quoted. Better yet, use a
mail client that gets this right out of the box.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2020-10-01 11:55 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-28 20:03 [Intel-gfx] [PATCH v2] drm/i915/display/ehl: Limit eDP to HBR2 José Roberto de Souza
2020-09-28 20:33 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display/ehl: Limit eDP to HBR2 (rev2) Patchwork
2020-09-29 1:31 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-09-30 15:56 ` [Intel-gfx] [PATCH v2] drm/i915/display/ehl: Limit eDP to HBR2 Surendrakumar Upadhyay, TejaskumarX
2020-09-30 20:21 ` Souza, Jose
2020-10-01 11:56 ` Jani Nikula [this message]
2020-09-30 16:14 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/display/ehl: Limit eDP to HBR2 (rev3) Patchwork
2020-10-03 4:23 ` [Intel-gfx] [PATCH v2] drm/i915/display/ehl: Limit eDP to HBR2 Matt Roper
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