From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 05/23] drm/i915: Issue engine resets onto idle engines
Date: Fri, 18 Jan 2019 14:06:32 +0200 [thread overview]
Message-ID: <87k1j2w4on.fsf@gaia.fi.intel.com> (raw)
In-Reply-To: <20190117143519.16086-6-chris@chris-wilson.co.uk>
Chris Wilson <chris@chris-wilson.co.uk> writes:
> Always perform the requested reset, even if we believe the engine is
> idle. Presumably there was a reason the caller wanted the reset, and in
> the near future we lose the easy tracking for whether the engine is
> idle.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/i915_reset.c | 4 ----
> .../gpu/drm/i915/selftests/intel_hangcheck.c | 22 +++++--------------
> 2 files changed, 6 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reset.c b/drivers/gpu/drm/i915/i915_reset.c
> index 064fc6da1512..d44b095e2860 100644
> --- a/drivers/gpu/drm/i915/i915_reset.c
> +++ b/drivers/gpu/drm/i915/i915_reset.c
> @@ -1063,10 +1063,6 @@ int i915_reset_engine(struct intel_engine_cs *engine, const char *msg)
> GEM_TRACE("%s flags=%lx\n", engine->name, error->flags);
> GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &error->flags));
>
> - if (i915_seqno_passed(intel_engine_get_seqno(engine),
> - intel_engine_last_submit(engine)))
> - return 0;
It seems you reinstate this later in this series. And
this patch doesn't apply as the i915_reset_engine doesn't
have the idle check.
-Mika
> -
> reset_prepare_engine(engine);
>
> if (msg)
> diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
> index 28144fd72550..9d0cc9d63a1e 100644
> --- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
> +++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
> @@ -449,8 +449,6 @@ static int __igt_reset_engine(struct drm_i915_private *i915, bool active)
>
> set_bit(I915_RESET_ENGINE + id, &i915->gpu_error.flags);
> do {
> - u32 seqno = intel_engine_get_seqno(engine);
> -
> if (active) {
> struct i915_request *rq;
>
> @@ -479,8 +477,6 @@ static int __igt_reset_engine(struct drm_i915_private *i915, bool active)
> break;
> }
>
> - GEM_BUG_ON(!rq->global_seqno);
> - seqno = rq->global_seqno - 1;
> i915_request_put(rq);
> }
>
> @@ -496,11 +492,10 @@ static int __igt_reset_engine(struct drm_i915_private *i915, bool active)
> break;
> }
>
> - reset_engine_count += active;
> if (i915_reset_engine_count(&i915->gpu_error, engine) !=
> - reset_engine_count) {
> - pr_err("%s engine reset %srecorded!\n",
> - engine->name, active ? "not " : "");
> + ++reset_engine_count) {
> + pr_err("%s engine reset not recorded!\n",
> + engine->name);
> err = -EINVAL;
> break;
> }
> @@ -728,7 +723,6 @@ static int __igt_reset_engines(struct drm_i915_private *i915,
>
> set_bit(I915_RESET_ENGINE + id, &i915->gpu_error.flags);
> do {
> - u32 seqno = intel_engine_get_seqno(engine);
> struct i915_request *rq = NULL;
>
> if (flags & TEST_ACTIVE) {
> @@ -756,9 +750,6 @@ static int __igt_reset_engines(struct drm_i915_private *i915,
> err = -EIO;
> break;
> }
> -
> - GEM_BUG_ON(!rq->global_seqno);
> - seqno = rq->global_seqno - 1;
> }
>
> err = i915_reset_engine(engine, NULL);
> @@ -795,10 +786,9 @@ static int __igt_reset_engines(struct drm_i915_private *i915,
>
> reported = i915_reset_engine_count(&i915->gpu_error, engine);
> reported -= threads[engine->id].resets;
> - if (reported != (flags & TEST_ACTIVE ? count : 0)) {
> - pr_err("i915_reset_engine(%s:%s): reset %lu times, but reported %lu, expected %lu reported\n",
> - engine->name, test_name, count, reported,
> - (flags & TEST_ACTIVE ? count : 0));
> + if (reported != count) {
> + pr_err("i915_reset_engine(%s:%s): reset %lu times, but reported %lu\n",
> + engine->name, test_name, count, reported);
> if (!err)
> err = -EINVAL;
> }
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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next prev parent reply other threads:[~2019-01-18 12:08 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-17 14:34 Swapping a single global interrupt handler for a herd Chris Wilson
2019-01-17 14:34 ` [PATCH 01/23] drm/i915: Make all GPU resets atomic Chris Wilson
2019-01-17 14:34 ` [PATCH 02/23] drm/i915/guc: Disable global reset Chris Wilson
2019-01-17 14:34 ` [PATCH 03/23] drm/i915: Remove GPU reset dependence on struct_mutex Chris Wilson
2019-01-17 14:34 ` [PATCH 04/23] drm/i915/selftests: Trim struct_mutex duration for set-wedged selftest Chris Wilson
2019-01-17 14:34 ` [PATCH 05/23] drm/i915: Issue engine resets onto idle engines Chris Wilson
2019-01-18 12:06 ` Mika Kuoppala [this message]
2019-01-17 14:34 ` [PATCH 06/23] drm/i915: Stop tracking MRU activity on VMA Chris Wilson
2019-01-17 14:34 ` [PATCH 07/23] drm/i915: Pull VM lists under the VM mutex Chris Wilson
2019-01-18 10:07 ` Tvrtko Ursulin
2019-01-17 14:34 ` [PATCH 08/23] drm/i915: Move vma lookup to its own lock Chris Wilson
2019-01-17 16:27 ` Tvrtko Ursulin
2019-01-17 16:31 ` Chris Wilson
2019-01-17 16:36 ` Chris Wilson
2019-01-17 16:51 ` Tvrtko Ursulin
2019-01-17 16:44 ` Chris Wilson
2019-01-17 14:34 ` [PATCH 09/23] drm/i915: Use b->irq_enable() as predicate for mock engine Chris Wilson
2019-01-17 16:44 ` Tvrtko Ursulin
2019-01-17 16:52 ` Chris Wilson
2019-01-17 18:00 ` Tvrtko Ursulin
2019-01-17 14:34 ` [PATCH 10/23] drm/i915/selftests: Allocate mock ring/timeline per context Chris Wilson
2019-01-17 14:34 ` [PATCH 11/23] drm/i915/selftests: Make evict tolerant of foreign objects Chris Wilson
2019-01-17 17:29 ` Tvrtko Ursulin
2019-01-18 11:23 ` Chris Wilson
2019-01-17 14:34 ` [PATCH 12/23] drm/i915: Always allocate an object/vma for the HWSP Chris Wilson
2019-01-17 14:34 ` [PATCH 13/23] drm/i915: Move list of timelines under its own lock Chris Wilson
2019-01-17 17:54 ` Tvrtko Ursulin
2019-01-18 11:31 ` Chris Wilson
2019-01-17 14:34 ` [PATCH 14/23] drm/i915: Introduce concept of per-timeline (context) HWSP Chris Wilson
2019-01-18 10:18 ` Tvrtko Ursulin
2019-01-17 14:34 ` [PATCH 15/23] drm/i915: Enlarge vma->pin_count Chris Wilson
2019-01-17 14:34 ` [PATCH 16/23] drm/i915: Allocate a status page for each timeline Chris Wilson
2019-01-18 11:19 ` Tvrtko Ursulin
2019-01-17 14:34 ` [PATCH 17/23] drm/i915: Share per-timeline HWSP using a slab suballocator Chris Wilson
2019-01-18 12:08 ` Tvrtko Ursulin
2019-01-17 14:34 ` [PATCH 18/23] drm/i915: Keep all partially allocated HWSP on a freelist Chris Wilson
2019-01-18 12:12 ` Mika Kuoppala
2019-01-18 12:25 ` Tvrtko Ursulin
2019-01-17 14:35 ` [PATCH 19/23] drm/i915: Track the context's seqno in its own timeline HWSP Chris Wilson
2019-01-18 14:10 ` Tvrtko Ursulin
2019-01-17 14:35 ` [PATCH 20/23] drm/i915: Identify active requests Chris Wilson
2019-01-17 14:35 ` [PATCH 21/23] drm/i915: Remove the intel_engine_notify tracepoint Chris Wilson
2019-01-17 14:35 ` [PATCH 22/23] drm/i915: Replace global breadcrumbs with per-context interrupt tracking Chris Wilson
2019-01-17 14:35 ` [PATCH 23/23] drm/i915: Drop fake breadcrumb irq Chris Wilson
2019-01-17 14:37 ` Swapping a single global interrupt handler for a herd Chris Wilson
2019-01-17 14:56 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/23] drm/i915: Make all GPU resets atomic Patchwork
2019-01-17 15:05 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-01-17 15:38 ` ✓ Fi.CI.BAT: success " Patchwork
2019-01-17 23:36 ` ✗ Fi.CI.IGT: failure " Patchwork
2019-01-17 23:41 ` Chris Wilson
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