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From: Jani Nikula <jani.nikula@linux.intel.com>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>,
	"Lucas De Marchi" <lucas.demarchi@intel.com>
Cc: intel-gfx@lists.freedesktop.org, Rodrigo Vivi <rodrigo.vivi@intel.com>
Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915: Move common mmio base out of private macros
Date: Thu, 02 Feb 2023 12:11:29 +0200	[thread overview]
Message-ID: <87lelg1ini.fsf@intel.com> (raw)
In-Reply-To: <Y9qjyrbuO8bWJgzv@intel.com>

On Wed, 01 Feb 2023, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Wed, Feb 01, 2023 at 09:26:29AM -0800, Lucas De Marchi wrote:
>> On Wed, Feb 01, 2023 at 02:09:54PM +0200, Ville Syrjälä wrote:
>> >On Wed, Feb 01, 2023 at 11:59:19AM +0200, Jani Nikula wrote:
>> >> On Tue, 31 Jan 2023, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
>> >> > -#define XELPDP_DP_AUX_CH_CTL(aux_ch)		_MMIO(_PICK(aux_ch, \
>> >> > -						       _DPA_AUX_CH_CTL, \
>> >> > -						       _DPB_AUX_CH_CTL, \
>> >> > -						       0, /* port/aux_ch C is non-existent */ \
>> >> > -						       _XELPDP_USBC1_AUX_CH_CTL, \
>> >> > -						       _XELPDP_USBC2_AUX_CH_CTL, \
>> >> > -						       _XELPDP_USBC3_AUX_CH_CTL, \
>> >> > -						       _XELPDP_USBC4_AUX_CH_CTL))
>> >> > +#define XELPDP_DP_AUX_CH_CTL(aux_ch)		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
>> >>
>> >> Note that only VLV and CHV have DISPLAY_MMIO_BASE() != 0.
>> >>
>> >> This is an XELPDP specific macro. Just drop the DISPLAY_MMIO_BASE() part
>> >> altogether, and you've removed an implicit dev_priv. Yay.
>> >>
>> >> This also makes me think we should probably add VLV/CHV specific
>> >> DP_AUX_CH_CTL and DP_AUX_CH_DATA macros that just add VLV_DISPLAY_BASE
>> >> directly, and use that to ditch the implicit dev_priv there too. This
>> >> approach doesn't work for everything, but the aux channel stuff is both
>> >> fairly limited use and already has if ladders to pick the
>> >> registers. Handling VLV/CHV separately is not a big deal.
>> >>
>> >> (DPLL on the other hand seems much harder to deal that way.)
>> >
>> >Most of the DPLL code should be have vlv/chv vs. rest specific
>> >codepaths. A quick scan says readout is perhaps the only exception.
>> 
>> and then remove display.mmio_offset since vlv/chv are the only ones
>> using it?
>
> There should tons of other registers still using it.

Yeah. It's just that DISPLAY_MMIO_BASE() was sprinkled around
gratuitously, when separate VLV/CHV specific macros would have been
better options. This is really case by case. Remove the requirement for
drm_i915_private access where it makes sense, and pass the pointer
explicitly elsewhere.

BR,
Jani.


-- 
Jani Nikula, Intel Open Source Graphics Center

  reply	other threads:[~2023-02-02 10:11 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-31 19:15 [Intel-gfx] [PATCH 1/2] drm/i915: Split _MMIO() for _PORT3()/_PIPE3() Lucas De Marchi
2023-01-31 19:15 ` [Intel-gfx] [PATCH 2/2] drm/i915: Move common mmio base out of private macros Lucas De Marchi
2023-02-01  9:59   ` Jani Nikula
2023-02-01 12:09     ` Ville Syrjälä
2023-02-01 17:26       ` Lucas De Marchi
2023-02-01 17:39         ` Ville Syrjälä
2023-02-02 10:11           ` Jani Nikula [this message]
2023-01-31 20:03 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Split _MMIO() for _PORT3()/_PIPE3() Patchwork
2023-01-31 21:55 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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