Re: [Intel-gfx] [PATCH] drm/i915/display: Remove check for low voltage sku for max dp source rate

[Jani Nikula <jani.nikula@linux.intel.com>]

On Tue, 26 Oct 2021, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
> The low voltage sku check can be ignored as OEMs need to consider that
> when designing the board and then put any limits in VBT.
>
> Same is now changed in Bspec pages.
>
> v2: Added debug print for combo PHY procmon reference values
> to get voltage configuration of combo PHY ports. (Imre)

Seems useful, but out of place in *this* patch.

>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_combo_phy.c    |  4 +++
>  drivers/gpu/drm/i915/display/intel_dp.c       | 32 ++-----------------
>  2 files changed, 7 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> index 634e8d449457..01ff86b3ff91 100644
> --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> @@ -112,6 +112,10 @@ static bool icl_verify_procmon_ref_values(struct drm_i915_private *dev_priv,
>  
>  	procmon = icl_get_procmon_ref_values(dev_priv, phy);
>  
> +	drm_dbg(&dev_priv->drm,

drm_dbg_kms please.

BR,
Jani.

> +		"Combo PHY %c PROCMON values : 0x%x, 0x%x, 0x%x\n",
> +		phy_name(phy), procmon->dw1, procmon->dw9, procmon->dw10);
> +
>  	ret = check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW1(phy),
>  			    (0xff << 16) | 0xff, procmon->dw1);
>  	ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW9(phy),
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index f5dc2126d140..693d7e097295 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -385,23 +385,13 @@ static int dg2_max_source_rate(struct intel_dp *intel_dp)
>  	return intel_dp_is_edp(intel_dp) ? 810000 : 1350000;
>  }
>  
> -static bool is_low_voltage_sku(struct drm_i915_private *i915, enum phy phy)
> -{
> -	u32 voltage;
> -
> -	voltage = intel_de_read(i915, ICL_PORT_COMP_DW3(phy)) & VOLTAGE_INFO_MASK;
> -
> -	return voltage == VOLTAGE_INFO_0_85V;
> -}
> -
>  static int icl_max_source_rate(struct intel_dp *intel_dp)
>  {
>  	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>  	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
>  	enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
>  
> -	if (intel_phy_is_combo(dev_priv, phy) &&
> -	    (is_low_voltage_sku(dev_priv, phy) || !intel_dp_is_edp(intel_dp)))
> +	if (intel_phy_is_combo(dev_priv, phy) && !intel_dp_is_edp(intel_dp))
>  		return 540000;
>  
>  	return 810000;
> @@ -409,23 +399,7 @@ static int icl_max_source_rate(struct intel_dp *intel_dp)
>  
>  static int ehl_max_source_rate(struct intel_dp *intel_dp)
>  {
> -	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> -	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> -	enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
> -
> -	if (intel_dp_is_edp(intel_dp) || is_low_voltage_sku(dev_priv, phy))
> -		return 540000;
> -
> -	return 810000;
> -}
> -
> -static int dg1_max_source_rate(struct intel_dp *intel_dp)
> -{
> -	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> -	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> -	enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
> -
> -	if (intel_phy_is_combo(i915, phy) && is_low_voltage_sku(i915, phy))
> +	if (intel_dp_is_edp(intel_dp))
>  		return 540000;
>  
>  	return 810000;
> @@ -468,7 +442,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
>  			max_rate = dg2_max_source_rate(intel_dp);
>  		else if (IS_ALDERLAKE_P(dev_priv) || IS_ALDERLAKE_S(dev_priv) ||
>  			 IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
> -			max_rate = dg1_max_source_rate(intel_dp);
> +			max_rate = 810000;
>  		else if (IS_JSL_EHL(dev_priv))
>  			max_rate = ehl_max_source_rate(intel_dp);
>  		else

-- 
Jani Nikula, Intel Open Source Graphics Center