From: Jani Nikula <jani.nikula@linux.intel.com>
To: Aditya Swarup <aditya.swarup@intel.com>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915/icl: Fix CRC mismatch error for DP link layer compliance
Date: Wed, 06 Mar 2019 10:52:30 +0200 [thread overview]
Message-ID: <87lg1sidv5.fsf@intel.com> (raw)
In-Reply-To: <20190306012654.1984-1-aditya.swarup@intel.com>
On Tue, 05 Mar 2019, Aditya Swarup <aditya.swarup@intel.com> wrote:
> Setting the pixel rounding bit to 1 in PIPE_CHICKEN register allows
> to passthrough FB pixels unmodified across pipe. This fixes the failures
> for DP link layer compliance tests 4.4.1.1, 4.4.1.2 & 4.4.1.3.
> (Lineage #1605353570)
>
> Cc: Clint Taylor <clinton.a.taylor@intel.com>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
> ---
> WA for ICL DP compliance. It fixes failing test in igt for crc mismatch
> wrt cursor plane. Can be searched using Lineage #1605353570.
>
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_display.c | 8 +++++++-
> 2 files changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c9b868347481..4713fbb3e021 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7663,6 +7663,7 @@ enum {
> #define _PIPEB_CHICKEN 0x71038
> #define _PIPEC_CHICKEN 0x72038
> #define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7)
> +#define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU (1 << 15)
Nitpick, see the big comment at the top of the file.
While at it, please move both of these bit macros below the
PIPE_CHICKEN() macro. Add two extra spaces after "#define", i.e. total
of three spaces. Order them highest to lowest bit.
BR,
Jani.
> #define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\
> _PIPEB_CHICKEN)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index d852cb282060..92be3476fef1 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3970,7 +3970,13 @@ static void icl_set_pipe_chicken(struct intel_crtc *crtc)
> * and rounding for per-pixel values 00 and 0xff
> */
> tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
> -
> + /*
> + * Display WA # 1605353570: icl
> + * Set the pixel rounding bit to 1 for allowing
> + * passthrough of Frame buffer pixels unmodified
> + * across pipe
> + */
> + tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
> I915_WRITE(PIPE_CHICKEN(pipe), tmp);
> }
--
Jani Nikula, Intel Open Source Graphics Center
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next prev parent reply other threads:[~2019-03-06 8:52 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-06 1:26 [PATCH] drm/i915/icl: Fix CRC mismatch error for DP link layer compliance Aditya Swarup
2019-03-06 2:18 ` ✓ Fi.CI.BAT: success for " Patchwork
2019-03-06 7:57 ` [PATCH] " Kahola, Mika
2019-03-06 8:52 ` Jani Nikula [this message]
2019-03-06 9:24 ` ✓ Fi.CI.IGT: success for " Patchwork
2019-03-07 2:14 ` [PATCH v2] " Aditya Swarup
2019-03-07 7:52 ` Kahola, Mika
2019-03-08 11:39 ` Saarinen, Jani
2019-03-08 12:49 ` Maarten Lankhorst
2019-03-07 2:29 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/icl: Fix CRC mismatch error for DP link layer compliance (rev2) Patchwork
2019-03-07 2:49 ` ✓ Fi.CI.BAT: success " Patchwork
2019-03-07 4:33 ` ✓ Fi.CI.IGT: " Patchwork
2019-03-08 14:28 ` ✓ Fi.CI.BAT: " Patchwork
2019-03-08 15:01 ` ✓ Fi.CI.IGT: " Patchwork
2019-03-08 16:20 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/icl: Fix CRC mismatch error for DP link layer compliance (rev3) Patchwork
2019-03-08 16:49 ` ✗ Fi.CI.BAT: failure " Patchwork
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