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From: Jani Nikula <jani.nikula@linux.intel.com>
To: Paulo Zanoni <przanoni@gmail.com>, intel-gfx@lists.freedesktop.org
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Subject: Re: [PATCH 7/8] drm/i915: try harder to find WR PLL clock settings
Date: Thu, 09 Aug 2012 13:56:40 +0300	[thread overview]
Message-ID: <87lihoe3kn.fsf@intel.com> (raw)
In-Reply-To: <1344446134-3704-8-git-send-email-przanoni@gmail.com>

On Wed, 08 Aug 2012, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> If we don't find the exact refresh rate, go with the next one. This
> makes some modes work for me. They won't have the best settings, but
> will at least have something. Just returning from this function when
> we don't find the perfect settings does not help us at all.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 33 ++++++++++++++-------------------
>  1 file changed, 14 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index ff03a3a..db242cf 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -267,7 +267,8 @@ struct wrpll_tmds_clock {
>  	u16 r2;		/* Reference divider */
>  };
>  
> -/* Table of matching values for WRPLL clocks programming for each frequency */
> +/* Table of matching values for WRPLL clocks programming for each frequency.
> + * The code assumes this table is sorted. */

I spotted some duplicate lines in the table. Perhaps you could remove
them while at it?

>  static const struct wrpll_tmds_clock wrpll_tmds_clock_table[] = {
>  	{19750,	38,	25,	18},
>  	{20000,	48,	32,	18},
> @@ -658,7 +659,7 @@ void intel_ddi_mode_set(struct drm_encoder *encoder,
>  	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
>  	int port = intel_hdmi->ddi_port;
>  	int pipe = intel_crtc->pipe;
> -	int p, n2, r2, valid=0;
> +	int p, n2, r2;
>  	u32 temp, i;
>  
>  	/* On Haswell, we need to enable the clocks and prepare DDI function to
> @@ -666,26 +667,20 @@ void intel_ddi_mode_set(struct drm_encoder *encoder,
>  	 */
>  	DRM_DEBUG_KMS("Preparing HDMI DDI mode for Haswell on port %c, pipe %c\n", port_name(port), pipe_name(pipe));
>  
> -	for (i=0; i < ARRAY_SIZE(wrpll_tmds_clock_table); i++) {
> -		if (crtc->mode.clock == wrpll_tmds_clock_table[i].clock) {
> -			p = wrpll_tmds_clock_table[i].p;
> -			n2 = wrpll_tmds_clock_table[i].n2;
> -			r2 = wrpll_tmds_clock_table[i].r2;
> +	for (i = 0; i < ARRAY_SIZE(wrpll_tmds_clock_table); i++)
> +		if (crtc->mode.clock <= wrpll_tmds_clock_table[i].clock)
> +			break;
>  
> -			DRM_DEBUG_KMS("WR PLL clock: found settings for %dKHz refresh rate: p=%d, n2=%d, r2=%d\n",
> -					crtc->mode.clock,
> -					p, n2, r2);

You drop this debug message. Is it intentional? The below DRM_INFO will
only be printed if an exact match is not found.

BR,
Jani.

> +	if (i == ARRAY_SIZE(wrpll_tmds_clock_table))
> +		i--;
>  
> -			valid = 1;
> -			break;
> -		}
> -	}
> +	if (wrpll_tmds_clock_table[i].clock != crtc->mode.clock)
> +		DRM_INFO("WR PLL: using settings for %dKHz on %dKHz mode\n",
> +			 wrpll_tmds_clock_table[i].clock, crtc->mode.clock);
>  
> -	if (!valid) {
> -		DRM_ERROR("Unable to find WR PLL clock settings for %dKHz refresh rate\n",
> -				crtc->mode.clock);
> -		return;
> -	}
> +	p = wrpll_tmds_clock_table[i].p;
> +	n2 = wrpll_tmds_clock_table[i].n2;
> +	r2 = wrpll_tmds_clock_table[i].r2;
>  
>  	/* Enable LCPLL if disabled */
>  	temp = I915_READ(LCPLL_CTL);
> -- 
> 1.7.11.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2012-08-09 10:53 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-08-08 17:15 [PATCH 0/8] Haswell HDMI fixes Paulo Zanoni
2012-08-08 17:15 ` [PATCH 1/8] drm/i915: fix pipe DDI mode select Paulo Zanoni
2012-08-08 17:15 ` [PATCH 2/8] drm/i915: set the DDI sync polarity bits Paulo Zanoni
2012-08-08 17:15 ` [PATCH 3/8] drm/i915: correctly set the DDI_FUNC_CTL bpc field Paulo Zanoni
2012-08-09  9:55   ` Jani Nikula
2012-08-09 16:40     ` Daniel Vetter
2012-08-09 16:46       ` Paulo Zanoni
2012-08-08 17:15 ` [PATCH 4/8] drm/i915: completely reset the value of DDI_FUNC_CTL Paulo Zanoni
2012-08-08 17:15 ` [PATCH 5/8] drm/i915: reindent Haswell register definitions Paulo Zanoni
2012-08-08 17:15 ` [PATCH 6/8] drm/i915: add parentheses around PIXCLK_GATE definitions Paulo Zanoni
2012-08-09 16:43   ` Daniel Vetter
2012-08-08 17:15 ` [PATCH 7/8] drm/i915: try harder to find WR PLL clock settings Paulo Zanoni
2012-08-09 10:56   ` Jani Nikula [this message]
2012-08-09 17:30     ` Paulo Zanoni
2012-08-09 17:38       ` Daniel Vetter
2012-08-08 17:15 ` [PATCH 8/8] drm/i915: try to use WR PLL 2 Paulo Zanoni
2012-08-09 11:32   ` Jani Nikula
2012-08-09 11:40 ` [PATCH 0/8] Haswell HDMI fixes Jani Nikula
2012-08-10 13:03 ` [PATCH] drm/i915: try harder to find WR PLL clock settings Paulo Zanoni
2012-08-10 13:18   ` Jani Nikula
2012-08-10 16:40     ` Daniel Vetter

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