Re: [Intel-gfx] [V2 1/1] drm/i915/debugfs: New debugfs for display clock frequencies

[Jani Nikula <jani.nikula@intel.com>]

On Wed, 12 Apr 2023, Jani Nikula <jani.nikula@intel.com> wrote:
> On Wed, 12 Apr 2023, Bhanuprakash Modem <bhanuprakash.modem@intel.com> wrote:
>> Instead of mixing display & non-display stuff together, move
>> display specific clock info to new debugfs. This patch will
>> create a new debugfs "i915_cdclk_info" to expose Current & Max
>> cdclk and Max pixel clock frequency info.
>>
>> Example:
>> $ cat /sys/kernel/debug/dri/0/i915_cdclk_info
>> Current CD clock frequency: 163200 kHz
>> Max CD clock frequency: 652800 kHz
>> Max pixel clock frequency: 1305600 kHz
>>
>> V2: - s/i915_display_clock_info/i915_cdclk_info/ (Jani)
>>     - Move the logic to intel_cdclk.c (Jani)
>>     - Don't remove info from i915_frequency_info (Jani)
>>
>> Cc: Jani Nikula <jani.nikula@intel.com>
>> Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_cdclk.c    | 25 +++++++++++++++++++
>>  drivers/gpu/drm/i915/display/intel_cdclk.h    |  1 +
>>  .../drm/i915/display/intel_display_debugfs.c  |  1 +
>>  3 files changed, 27 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> index 084a483f9776..c3ad7837fa09 100644
>> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> @@ -3235,6 +3235,31 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
>>  	return freq;
>>  }
>>  
>> +static int i915_cdclk_info_show(struct seq_file *m, void *unused)
>> +{
>> +	struct drm_i915_private *i915 = m->private;
>> +
>> +	drm_modeset_lock_all(&i915->drm);
>
> Mmmh, I wonder how important that really is?

With the locking removed, this is

Reviewed-by: Jani Nikula <jani.nikula@intel.com>



>
> BR,
> Jani.
>
>
>> +
>> +	seq_printf(m, "Current CD clock frequency: %d kHz\n", i915->display.cdclk.hw.cdclk);
>> +	seq_printf(m, "Max CD clock frequency: %d kHz\n", i915->display.cdclk.max_cdclk_freq);
>> +	seq_printf(m, "Max pixel clock frequency: %d kHz\n", i915->max_dotclk_freq);
>> +
>> +	drm_modeset_unlock_all(&i915->drm);
>> +
>> +	return 0;
>> +}
>> +
>> +DEFINE_SHOW_ATTRIBUTE(i915_cdclk_info);
>> +
>> +void intel_cdclk_debugfs_register(struct drm_i915_private *i915)
>> +{
>> +	struct drm_minor *minor = i915->drm.primary;
>> +
>> +	debugfs_create_file("i915_cdclk_info", 0444, minor->debugfs_root,
>> +			    i915, &i915_cdclk_info_fops);
>> +}
>> +
>>  static const struct intel_cdclk_funcs mtl_cdclk_funcs = {
>>  	.get_cdclk = bxt_get_cdclk,
>>  	.set_cdclk = bxt_set_cdclk,
>> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
>> index 51e2f6a11ce4..48fd7d39e0cd 100644
>> --- a/drivers/gpu/drm/i915/display/intel_cdclk.h
>> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
>> @@ -82,5 +82,6 @@ intel_atomic_get_cdclk_state(struct intel_atomic_state *state);
>>  	to_intel_cdclk_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->display.cdclk.obj))
>>  
>>  int intel_cdclk_init(struct drm_i915_private *dev_priv);
>> +void intel_cdclk_debugfs_register(struct drm_i915_private *i915);
>>  
>>  #endif /* __INTEL_CDCLK_H__ */
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> index 45113ae107ba..abd16a2b1f7a 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> @@ -1094,6 +1094,7 @@ void intel_display_debugfs_register(struct drm_i915_private *i915)
>>  				 ARRAY_SIZE(intel_display_debugfs_list),
>>  				 minor->debugfs_root, minor);
>>  
>> +	intel_cdclk_debugfs_register(i915);
>>  	intel_dmc_debugfs_register(i915);
>>  	intel_fbc_debugfs_register(i915);
>>  	intel_hpd_debugfs_register(i915);

-- 
Jani Nikula, Intel Open Source Graphics Center