From: Jani Nikula <jani.nikula@intel.com>
To: Madhav Chauhan <madhav.chauhan@intel.com>,
intel-gfx@lists.freedesktop.org
Cc: paulo.r.zanoni@intel.com, rodrigo.vivi@intel.com
Subject: Re: [PATCH v2 05/20] drm/i915/icl: Define PORT_CL_DW_10 register
Date: Wed, 04 Jul 2018 17:38:23 +0300 [thread overview]
Message-ID: <87muv7oylc.fsf@intel.com> (raw)
In-Reply-To: <1530622074-28307-6-git-send-email-madhav.chauhan@intel.com>
On Tue, 03 Jul 2018, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> This register used to power down individual lanes for
> DDI/DSI ports. Bitfields to power up/down various
> combinations of lanes are also added in this patch.
>
> v2: Review comments from Jani N
> - Use override instead of "override" for bitfields
> - Define mask for override bitfield
> - Define PWR_DOWN_LN* macros shifted in place
>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index dfd603c..3fa8f02 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1704,6 +1704,26 @@ enum i915_power_well_id {
> #define ICL_PORT_CL_DW5(port) _MMIO_PORT(port, _ICL_PORT_CL_DW5_A, \
> _ICL_PORT_CL_DW5_B)
>
> +#define _CNL_PORT_CL_DW10_A 0x162028
> +#define _ICL_PORT_CL_DW10_B 0x6c028
> +#define ICL_PORT_CL_DW10(port) _MMIO_PORT(port, \
> + _CNL_PORT_CL_DW10_A, \
> + _ICL_PORT_CL_DW10_B)
> +#define PG_SEQ_DELAY_OVERRIDE_MASK (3 << 25)
> +#define PG_SEQ_DELAY_OVERRIDE_SHIFT 25
> +#define PG_SEQ_DELAY_OVERRIDE_ENABLE (1 << 24)
> +#define PWR_UP_ALL_LANES (0x0 << 4)
> +#define PWR_DOWN_LN_3_2_1 (0xe << 4)
> +#define PWR_DOWN_LN_3_2 (0xc << 4)
> +#define PWR_DOWN_LN_3 (0x8 << 4)
> +#define PWR_DOWN_LN_2_1_0 (0x7 << 4)
> +#define PWR_DOWN_LN_1_0 (0x3 << 4)
> +#define PWR_DOWN_LN_1 (0x2 << 4)
> +#define PWR_DOWN_LN_3_1 (0xa << 4)
> +#define PWR_DOWN_LN_3_1_0 (0xb << 4)
> +#define PWR_DOWN_LN_MASK (0xf0 << 4)
Should be (0xf << 4).
With that fixed,
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> +#define PWR_DOWN_LN_SHIFT 4
> +
> #define _PORT_CL1CM_DW9_A 0x162024
> #define _PORT_CL1CM_DW9_BC 0x6C024
> #define IREF0RC_OFFSET_SHIFT 8
--
Jani Nikula, Intel Open Source Graphics Center
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next prev parent reply other threads:[~2018-07-04 14:38 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-03 12:47 [PATCH v2 00/20] ICELAKE DSI DRIVER Madhav Chauhan
2018-07-03 12:47 ` [PATCH v2 01/20] drm/i915/icl: Define register for DSI PLL Madhav Chauhan
2018-07-03 12:47 ` [PATCH v2 02/20] drm/i915/icl: Program DSI Escape clock Divider Madhav Chauhan
2018-07-03 12:47 ` [PATCH v2 03/20] drm/i915/icl: Define DSI mode ctl register Madhav Chauhan
2018-07-03 12:47 ` [PATCH v2 04/20] drm/i915/icl: Enable DSI IO power Madhav Chauhan
2018-07-03 12:47 ` [PATCH v2 05/20] drm/i915/icl: Define PORT_CL_DW_10 register Madhav Chauhan
2018-07-04 14:38 ` Jani Nikula [this message]
2018-07-04 15:11 ` Chauhan, Madhav
2018-07-03 12:47 ` [PATCH v2 06/20] drm/i915/icl: Power down unused DSI lanes Madhav Chauhan
2018-07-03 12:47 ` [PATCH v2 07/20] drm/i915/icl: Define AUX lane registers for Port A/B Madhav Chauhan
2018-07-04 14:54 ` Jani Nikula
2018-07-05 9:43 ` Chauhan, Madhav
2018-07-03 12:47 ` [PATCH v2 08/20] drm/i915/icl: Configure lane sequencing of combo phy transmitter Madhav Chauhan
2018-07-03 12:47 ` [PATCH v2 09/20] drm/i915/icl: DSI vswing programming sequence Madhav Chauhan
2018-07-03 12:47 ` [PATCH v2 10/20] drm/i915/icl: Enable DDI Buffer Madhav Chauhan
2018-07-03 12:47 ` [PATCH v2 11/20] drm/i915/icl: Define T_INIT_MASTER registers Madhav Chauhan
2018-07-03 12:47 ` [PATCH v2 12/20] drm/i915/icl: Program " Madhav Chauhan
2018-07-03 12:47 ` [PATCH v2 13/20] drm/i915/icl: Define data/clock lanes dphy timing registers Madhav Chauhan
2018-07-03 12:47 ` [PATCH v2 14/20] drm/i915/icl: Program DSI clock and data lane timing params Madhav Chauhan
2018-07-03 12:47 ` [PATCH v2 15/20] drm/i915/icl: Define TA_TIMING_PARAM registers Madhav Chauhan
2018-07-03 12:47 ` [PATCH v2 16/20] drm/i915/icl: Program " Madhav Chauhan
2018-07-03 12:47 ` [PATCH v2 17/20] drm/i915/icl: Get DSI transcoder for a given port Madhav Chauhan
2018-07-03 12:47 ` [PATCH v2 18/20] drm/i915/icl: Add macros for MMIO of DSI transcoder registers Madhav Chauhan
2018-07-03 12:47 ` [PATCH v2 19/20] drm/i915/icl: Define TRANS_DSI_FUNC_CONF register Madhav Chauhan
2018-07-03 12:47 ` [PATCH v2 20/20] drm/i915/icl: Configure DSI transcoders Madhav Chauhan
2018-07-03 13:52 ` ✗ Fi.CI.CHECKPATCH: warning for ICELAKE DSI DRIVER (rev2) Patchwork
2018-07-03 13:59 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-07-03 14:15 ` ✓ Fi.CI.BAT: success " Patchwork
2018-07-03 22:48 ` ✓ Fi.CI.IGT: " Patchwork
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