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From: "Dixit, Ashutosh" <ashutosh.dixit@intel.com>
To: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 1/3] drm/i915/perf: Subtract gtt_offset from hw_tail
Date: Tue, 12 Sep 2023 19:20:19 -0700	[thread overview]
Message-ID: <87o7i6u84c.wl-ashutosh.dixit@intel.com> (raw)
In-Reply-To: <ZQEPfDuOr0bC/s+K@unerlige-ril>

On Tue, 12 Sep 2023 18:25:16 -0700, Umesh Nerlige Ramappa wrote:
>

Hi Umesh,

> On Fri, Sep 08, 2023 at 06:16:24PM -0700, Ashutosh Dixit wrote:
> > The code in oa_buffer_check_unlocked() is correct only if the OA buffer is
> > 16 MB aligned (which seems to be the case today in i915). However when the
> > 16 MB alignment is dropped, when we "Subtract partial amount off the tail",
> > the "& (OA_BUFFER_SIZE - 1)" operation in OA_TAKEN() will result in an
> > incorrect hw_tail value.
> >
> > Therefore hw_tail must be brought to the same base as head and read_tail
> > prior to OA_TAKEN by subtracting gtt_offset from hw_tail.
> >
> > Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_perf.c | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> > index 018f42fff4cc0..ec0fc2934045a 100644
> > --- a/drivers/gpu/drm/i915/i915_perf.c
> > +++ b/drivers/gpu/drm/i915/i915_perf.c
> > @@ -565,6 +565,7 @@ static bool oa_buffer_check_unlocked(struct i915_perf_stream *stream)
> >	partial_report_size %= report_size;
> >
> >	/* Subtract partial amount off the tail */
> > +	hw_tail -= gtt_offset;
> >	hw_tail = OA_TAKEN(hw_tail, partial_report_size);
>
> I see partial_report_size is a value in the 0 - report_size range and it
> may not have the gtt_offset added to it, so I guess the OA_TAKEN may result
> in a bad value, but I am not able to visualize what the specific issue
> is. Can you please provide an example with numbers?
>
> Also, slightly confused about the need for this patch. Are we dropping the
> 16 MB alignment for some reason?  If not, I suggest we can add this patch
> later with any series that drops it.

I found this issue when porting i915 OA code to XE (which doesn't have 16
MB alignment), I had to make this fix in XE in order to get things to work.

In any case, as you already pointed out, Patch 2 overrides Patch 1, so
let's just drop Patch 1.

Thanks.
--
Ashutosh

  reply	other threads:[~2023-09-13  2:20 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-09  1:16 [Intel-gfx] [PATCH 0/3] drm/i915/perf: A few fixes and enhancements Ashutosh Dixit
2023-09-09  1:16 ` [Intel-gfx] [PATCH 1/3] drm/i915/perf: Subtract gtt_offset from hw_tail Ashutosh Dixit
2023-09-13  1:25   ` Umesh Nerlige Ramappa
2023-09-13  2:20     ` Dixit, Ashutosh [this message]
2023-09-09  1:16 ` [Intel-gfx] [PATCH 2/3] drm/i915/perf: Remove gtt_offset from stream->oa_buffer.head/.tail Ashutosh Dixit
2023-09-13  1:36   ` Umesh Nerlige Ramappa
2023-09-09  1:16 ` [Intel-gfx] [PATCH 3/3] drm/i915/perf: Initialize gen12 OA buffer unconditionally Ashutosh Dixit
2023-09-09  1:24   ` Dixit, Ashutosh
2023-09-13  1:46     ` Umesh Nerlige Ramappa
2023-09-13 16:59       ` Dixit, Ashutosh

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