From: Jani Nikula <jani.nikula@intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v3 03/17] drm/i915: Extract HAS_DOUBLE_BUFFERED_M_N()
Date: Mon, 20 Jun 2022 21:07:30 +0300 [thread overview]
Message-ID: <87o7ynryxp.fsf@intel.com> (raw)
In-Reply-To: <20220620175210.28788-4-ville.syrjala@linux.intel.com>
On Mon, 20 Jun 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We have a couple of places that want to make distinction between
> double buffered M/N registers vs. the split M1/N1+M2/N2 registers.
> Add a helper for that.
>
> v2: Turn into a HAS_ macro (Jani)
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com> #v1
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
I'm fine with this, obviously, but also started wondering about the
other direction [1].
BR,
Jani.
[1] https://patchwork.freedesktop.org/patch/msgid/dc7e02a24fc231ef0fa3c4e84c01ebf19d61de2f.1655748056.git.jani.nikula@intel.com
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
> drivers/gpu/drm/i915/display/intel_dp.c | 3 +--
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> 3 files changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 6b549aadca13..0384af821ee5 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5760,7 +5760,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> PIPE_CONF_CHECK_I(lane_count);
> PIPE_CONF_CHECK_X(lane_lat_optim_mask);
>
> - if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) {
> + if (HAS_DOUBLE_BUFFERED_M_N(dev_priv)) {
> PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
> } else {
> PIPE_CONF_CHECK_M_N(dp_m_n);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index e0891b31f089..cf7e4e105891 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1868,8 +1868,7 @@ intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
> static bool cpu_transcoder_has_drrs(struct drm_i915_private *i915,
> enum transcoder cpu_transcoder)
> {
> - /* M1/N1 is double buffered */
> - if (DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915))
> + if (HAS_DOUBLE_BUFFERED_M_N(i915))
> return true;
>
> return intel_cpu_transcoder_has_m2_n2(i915, cpu_transcoder);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index c22f29c3faa0..805ae6ca7486 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1252,6 +1252,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst)
> #define HAS_DP20(dev_priv) (IS_DG2(dev_priv))
>
> +#define HAS_DOUBLE_BUFFERED_M_N(dev_priv) (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
> +
> #define HAS_CDCLK_CRAWL(dev_priv) (INTEL_INFO(dev_priv)->display.has_cdclk_crawl)
> #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi)
> #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
--
Jani Nikula, Intel Open Source Graphics Center
next prev parent reply other threads:[~2022-06-20 18:08 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-20 17:51 [Intel-gfx] [PATCH v3 00/17] drm/i915: Make fastset not suck and allow seamless M/N changes Ville Syrjala
2022-06-20 17:51 ` [Intel-gfx] [PATCH v3 01/17] drm/i915: Relocate intel_crtc_dotclock() Ville Syrjala
2022-06-20 17:51 ` [Intel-gfx] [PATCH v3 02/17] drm/i915: Shuffle some PLL code around Ville Syrjala
2022-06-20 17:51 ` [Intel-gfx] [PATCH v3 03/17] drm/i915: Extract HAS_DOUBLE_BUFFERED_M_N() Ville Syrjala
2022-06-20 18:07 ` Jani Nikula [this message]
2022-06-20 17:51 ` [Intel-gfx] [PATCH v3 04/17] drm/i915/dsi: Extract {vlv, bxt}_get_pclk() Ville Syrjala
2022-09-02 6:00 ` Kahola, Mika
2022-06-20 17:51 ` [Intel-gfx] [PATCH v3 05/17] drm/i915: Do .crtc_compute_clock() earlier Ville Syrjala
2022-06-20 17:51 ` [Intel-gfx] [PATCH v3 06/17] drm/i915: Reassign DPLLs only for crtcs going throug .compute_config() Ville Syrjala
2022-06-20 17:52 ` [Intel-gfx] [PATCH v3 07/17] drm/i915: Feed the DPLL output freq back into crtc_state Ville Syrjala
2022-06-20 17:52 ` [Intel-gfx] [PATCH v3 08/17] drm/i915: Compute clocks earlier Ville Syrjala
2022-06-20 17:52 ` [Intel-gfx] [PATCH v3 09/17] drm/i915: Make M/N checks non-fuzzy Ville Syrjala
2022-06-20 17:52 ` [Intel-gfx] [PATCH v3 10/17] drm/i915: Make all clock " Ville Syrjala
2022-06-20 17:52 ` [Intel-gfx] [PATCH v3 11/17] drm/i915: Set active dpll early for icl+ Ville Syrjala
2022-06-20 17:52 ` [Intel-gfx] [PATCH v3 12/17] drm/i915: Nuke fastet state copy hacks Ville Syrjala
2022-06-20 17:52 ` [Intel-gfx] [PATCH v3 13/17] drm/i915: Skip intel_modeset_pipe_config_late() if the pipe is not enabled Ville Syrjala
2022-06-20 17:52 ` [Intel-gfx] [PATCH v3 14/17] drm/i915: Add intel_panel_highest_mode() Ville Syrjala
2022-06-20 17:52 ` [Intel-gfx] [PATCH v3 15/17] drm/i915: Allow M/N change during fastset on bdw+ Ville Syrjala
2022-09-01 8:25 ` Kahola, Mika
2022-06-20 17:52 ` [Intel-gfx] [PATCH v3 16/17] drm/i915: Use a fixed N value always Ville Syrjala
2022-06-20 17:52 ` [Intel-gfx] [PATCH v3 17/17] drm/i915: Round TMDS clock to nearest Ville Syrjala
2022-06-20 22:32 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Make fastset not suck and allow seamless M/N changes (rev6) Patchwork
2022-06-20 22:32 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-06-20 22:54 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-06-21 12:28 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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