From: Jani Nikula <jani.nikula@linux.intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 06/13] drm/i915: Polish drrs type enum
Date: Thu, 10 Mar 2022 11:38:50 +0200 [thread overview]
Message-ID: <87pmmuxi39.fsf@intel.com> (raw)
In-Reply-To: <20220310004802.16310-7-ville.syrjala@linux.intel.com>
On Thu, 10 Mar 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Make the drrs type enum less convoluted.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Might've called it INTEL_DRRS_* but *shrug*.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_bios.c | 10 +++++-----
> drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 +-
> drivers/gpu/drm/i915/display/intel_drrs.c | 10 +++++-----
> drivers/gpu/drm/i915/i915_drv.h | 12 ++++++------
> 4 files changed, 17 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
> index 93dc32fb3e40..c7afe19dd44a 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -257,16 +257,16 @@ parse_panel_options(struct drm_i915_private *i915,
> */
> switch (drrs_mode) {
> case 0:
> - i915->vbt.drrs_type = STATIC_DRRS_SUPPORT;
> + i915->vbt.drrs_type = DRRS_TYPE_STATIC;
> drm_dbg_kms(&i915->drm, "DRRS supported mode is static\n");
> break;
> case 2:
> - i915->vbt.drrs_type = SEAMLESS_DRRS_SUPPORT;
> + i915->vbt.drrs_type = DRRS_TYPE_SEAMLESS;
> drm_dbg_kms(&i915->drm,
> "DRRS supported mode is seamless\n");
> break;
> default:
> - i915->vbt.drrs_type = DRRS_NOT_SUPPORTED;
> + i915->vbt.drrs_type = DRRS_TYPE_NONE;
> drm_dbg_kms(&i915->drm,
> "DRRS not supported (VBT input)\n");
> break;
> @@ -740,7 +740,7 @@ parse_driver_features(struct drm_i915_private *i915,
> * driver->drrs_enabled=false
> */
> if (!driver->drrs_enabled)
> - i915->vbt.drrs_type = DRRS_NOT_SUPPORTED;
> + i915->vbt.drrs_type = DRRS_TYPE_NONE;
>
> i915->vbt.psr.enable = driver->psr_enabled;
> }
> @@ -769,7 +769,7 @@ parse_power_conservation_features(struct drm_i915_private *i915,
> * power->drrs & BIT(panel_type)=false
> */
> if (!(power->drrs & BIT(panel_type)))
> - i915->vbt.drrs_type = DRRS_NOT_SUPPORTED;
> + i915->vbt.drrs_type = DRRS_TYPE_NONE;
>
> if (bdb->version >= 232)
> i915->vbt.edp.hobl = power->hobl & BIT(panel_type);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 41b81d5dd5f4..28414472110e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -1163,7 +1163,7 @@ static void drrs_status_per_crtc(struct seq_file *m,
> seq_printf(m, "%s:\n", connector->name);
>
> if (connector->connector_type == DRM_MODE_CONNECTOR_eDP &&
> - drrs->type == SEAMLESS_DRRS_SUPPORT)
> + drrs->type == DRRS_TYPE_SEAMLESS)
> supported = true;
>
> seq_printf(m, "\tDRRS Supported: %s\n", str_yes_no(supported));
> diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c b/drivers/gpu/drm/i915/display/intel_drrs.c
> index 5b3711fe0674..7c4a3ecee93a 100644
> --- a/drivers/gpu/drm/i915/display/intel_drrs.c
> +++ b/drivers/gpu/drm/i915/display/intel_drrs.c
> @@ -65,7 +65,7 @@ static bool can_enable_drrs(struct intel_connector *connector,
> return false;
>
> return connector->panel.downclock_mode &&
> - i915->drrs.type == SEAMLESS_DRRS_SUPPORT;
> + i915->drrs.type == DRRS_TYPE_SEAMLESS;
> }
>
> void
> @@ -155,7 +155,7 @@ static void intel_drrs_set_state(struct drm_i915_private *dev_priv,
> return;
> }
>
> - if (dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT) {
> + if (dev_priv->drrs.type != DRRS_TYPE_SEAMLESS) {
> drm_dbg_kms(&dev_priv->drm, "Only Seamless DRRS supported.\n");
> return;
> }
> @@ -274,7 +274,7 @@ intel_drrs_update(struct intel_dp *intel_dp,
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>
> - if (dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT)
> + if (dev_priv->drrs.type != DRRS_TYPE_SEAMLESS)
> return;
>
> mutex_lock(&dev_priv->drrs.mutex);
> @@ -329,7 +329,7 @@ static void intel_drrs_frontbuffer_update(struct drm_i915_private *dev_priv,
> struct drm_crtc *crtc;
> enum pipe pipe;
>
> - if (dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT)
> + if (dev_priv->drrs.type != DRRS_TYPE_SEAMLESS)
> return;
>
> cancel_delayed_work(&dev_priv->drrs.work);
> @@ -449,7 +449,7 @@ intel_drrs_init(struct intel_connector *connector,
> return NULL;
> }
>
> - if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
> + if (dev_priv->vbt.drrs_type != DRRS_TYPE_SEAMLESS) {
> drm_dbg_kms(&dev_priv->drm,
> "[CONNECTOR:%d:%s] DRRS not supported according to VBT\n",
> connector->base.base.id, connector->base.name);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 020c5f7602a2..0fc5d7e447b9 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -207,10 +207,10 @@ enum drrs_refresh_rate_type {
> DRRS_MAX_RR, /* RR count */
> };
>
> -enum drrs_support_type {
> - DRRS_NOT_SUPPORTED = 0,
> - STATIC_DRRS_SUPPORT = 1,
> - SEAMLESS_DRRS_SUPPORT = 2
> +enum drrs_type {
> + DRRS_TYPE_NONE,
> + DRRS_TYPE_STATIC,
> + DRRS_TYPE_SEAMLESS,
> };
>
> struct i915_drrs {
> @@ -219,7 +219,7 @@ struct i915_drrs {
> struct intel_dp *dp;
> unsigned busy_frontbuffer_bits;
> enum drrs_refresh_rate_type refresh_rate_type;
> - enum drrs_support_type type;
> + enum drrs_type type;
> };
>
> #define QUIRK_LVDS_SSC_DISABLE (1<<1)
> @@ -349,7 +349,7 @@ struct intel_vbt_data {
> bool override_afc_startup;
> u8 override_afc_startup_val;
>
> - enum drrs_support_type drrs_type;
> + enum drrs_type drrs_type;
>
> struct {
> int rate;
--
Jani Nikula, Intel Open Source Graphics Center
next prev parent reply other threads:[~2022-03-10 9:38 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-10 0:47 [Intel-gfx] [PATCH 00/13] drm/i915: DRRS fixes/cleanups and start of static DRRS Ville Syrjala
2022-03-10 0:47 ` [Intel-gfx] [PATCH 01/13] drm/i915: Fix up some DRRS type checks Ville Syrjala
2022-03-10 9:25 ` Jani Nikula
2022-03-10 0:47 ` [Intel-gfx] [PATCH 02/13] drm/i915: Constify intel_drrs_init() args Ville Syrjala
2022-03-10 9:25 ` Jani Nikula
2022-03-10 0:47 ` [Intel-gfx] [PATCH 03/13] drm/i915: Pimp DRRS debugs Ville Syrjala
2022-03-10 9:27 ` Jani Nikula
2022-03-10 0:47 ` [Intel-gfx] [PATCH 04/13] drm/i915: Read DRRS MSA timing delay from VBT Ville Syrjala
2022-03-10 9:32 ` Jani Nikula
2022-03-10 0:47 ` [Intel-gfx] [PATCH 05/13] drm/i915: Program MSA timing delay on ilk/snb/ivb Ville Syrjala
2022-03-10 9:37 ` Jani Nikula
2022-03-10 0:47 ` [Intel-gfx] [PATCH 06/13] drm/i915: Polish drrs type enum Ville Syrjala
2022-03-10 9:38 ` Jani Nikula [this message]
2022-03-10 0:47 ` [Intel-gfx] [PATCH 07/13] drm/i915: Clean up DRRS refresh rate enum Ville Syrjala
2022-03-10 9:43 ` Jani Nikula
2022-03-10 0:47 ` [Intel-gfx] [PATCH 08/13] drm/i915: Rename PIPECONF refresh select bits Ville Syrjala
2022-03-10 9:44 ` Jani Nikula
2022-03-10 0:47 ` [Intel-gfx] [PATCH 09/13] drm/i915: Stash DRRS state under intel_crtc Ville Syrjala
2022-03-10 10:53 ` Jani Nikula
2022-03-10 11:12 ` Ville Syrjälä
2022-03-10 17:45 ` Souza, Jose
2022-03-10 18:29 ` Ville Syrjälä
2022-03-10 0:47 ` [Intel-gfx] [PATCH 10/13] drm/i915: Move DRRS enable/disable higher up Ville Syrjala
2022-03-10 9:54 ` Jani Nikula
2022-03-10 0:48 ` [Intel-gfx] [PATCH 11/13] drm/i915: Enable eDP DRRS on ilk/snb port A Ville Syrjala
2022-03-10 9:59 ` Jani Nikula
2022-03-10 0:48 ` [Intel-gfx] [PATCH 12/13] drm/i915: Introduce intel_panel_{fixed, downclock}_mode() Ville Syrjala
2022-03-10 10:09 ` Jani Nikula
2022-03-10 0:48 ` [Intel-gfx] [PATCH 13/13] drm/i915: Implement static DRRS Ville Syrjala
2022-03-10 10:30 ` Jani Nikula
2022-03-10 11:01 ` Ville Syrjälä
2022-03-10 11:26 ` Jani Nikula
2022-03-10 1:28 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: DRRS fixes/cleanups and start of " Patchwork
2022-03-10 1:29 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-03-10 2:06 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-03-10 9:14 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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