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From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] drm/i915/execlists: Enable timeslice on partial virtual engine dequeue
Date: Thu, 05 Mar 2020 15:13:09 +0200	[thread overview]
Message-ID: <87pndr3py2.fsf@gaia.fi.intel.com> (raw)
In-Reply-To: <8736an58ql.fsf@gaia.fi.intel.com>

Mika Kuoppala <mika.kuoppala@linux.intel.com> writes:

> Chris Wilson <chris@chris-wilson.co.uk> writes:
>
>> If we stop filling the ELSP due to an incompatible virtual engine
>> request, check if we should enable the timeslice on behalf of the queue.
>>
>
> Leaves me pondering more of the why.
>
> So that on these boundaries also, the last rq gets subdued to
> a timeslice and not get a free run?

I got some confirmations on irc. Yes this for that.
The commit message could be augmented on the why emphasis!

>
>> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>> ---
>>  drivers/gpu/drm/i915/gt/intel_lrc.c | 21 ++++++++++++++++-----
>>  1 file changed, 16 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
>> index 5da86a40434c..954bd4797482 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
>> @@ -1802,6 +1802,20 @@ static void set_timeslice(struct intel_engine_cs *engine)
>>  	set_timer_ms(&engine->execlists.timer, active_timeslice(engine));
>>  }
>>  
>> +static void start_timeslice(struct intel_engine_cs *engine,
>> +			    struct i915_request *last)
>> +{
>> +	struct intel_engine_execlists *execlists = &engine->execlists;
>> +
>> +	/* As we are returning early, update the hint from the queue */
>> +	execlists->switch_priority_hint =
>> +		max(execlists->queue_priority_hint,
>> +		    execlists->switch_priority_hint);

Still not completely unclear how the all hints play together
but the comment holds true, we bail out early.

>> +
>> +	if (!execlists->timer.expires && need_timeslice(engine, last))
>> +		set_timer_ms(&execlists->timer, timeslice(engine));
>> +}
>> +
>>  static void record_preemption(struct intel_engine_execlists *execlists)
>>  {
>>  	(void)I915_SELFTEST_ONLY(execlists->preempt_hang.count++);
>> @@ -1965,11 +1979,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
>>  				 * Even if ELSP[1] is occupied and not worthy
>>  				 * of timeslices, our queue might be.
>>  				 */
>> -				if (!execlists->timer.expires &&
>> -				    need_timeslice(engine, last))
>> -					set_timer_ms(&execlists->timer,
>> -						     timeslice(engine));
>> -
>> +				start_timeslice(engine, last);
>>  				return;
>>  			}
>>  		}
>> @@ -2004,6 +2014,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
>>  
>>  			if (last && !can_merge_rq(last, rq)) {
>>  				spin_unlock(&ve->base.active.lock);
>> +				start_timeslice(engine, last);
>>  				return; /* leave this for another */
>
> for another interrupt?

For another veng. The comment might have already been augmented.

Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

> -Mika
>
>>  			}
>>  
>> -- 
>> 2.25.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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  reply	other threads:[~2020-03-05 13:14 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-05  7:35 [Intel-gfx] [PATCH] drm/i915/execlists: Enable timeslice on partial virtual engine dequeue Chris Wilson
2020-03-05 11:41 ` Mika Kuoppala
2020-03-05 13:13   ` Mika Kuoppala [this message]
2020-03-05 19:50 ` [Intel-gfx] ✗ Fi.CI.DOCS: warning for " Patchwork
2020-03-05 20:28 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-03-06 10:57 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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