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From: Jani Nikula <jani.nikula@linux.intel.com>
To: Andi Kleen <ak@linux.intel.com>
Cc: airlied@linux.ie, intel-gfx@lists.freedesktop.org,
	dri-devel@lists.freedesktop.org, Andi Kleen <andi@firstfloor.org>
Subject: Re: [Intel-gfx] [PATCH] i915: Increase *_latency array size
Date: Wed, 05 May 2021 09:32:58 +0300	[thread overview]
Message-ID: <87r1ily9k5.fsf@intel.com> (raw)
In-Reply-To: <20210505033737.1282652-1-ak@linux.intel.com>

On Tue, 04 May 2021, Andi Kleen <ak@linux.intel.com> wrote:
> From: Andi Kleen <andi@firstfloor.org>
>
> Newer gcc prints the following warning:
>
> drivers/gpu/drm/i915/intel_pm.c:3057:9: warning: ‘intel_print_wm_latency’ reading 16 bytes from a region of size 10 [-Wstringop-overread]
> and some other related warnings in similar functions.
>
> gcc has a point here. Some of the latency arrays only have 5 members,
> but print_wm_latency may read up to max_level returned by ilk_wm_max_level,
> which can be upto 7 for the >= GEN9 case.
>
> So it will read some fields beyond the array.
>
> Increase all the latency fields to 8 members, which is enough for SKL.
>
> I don't know if they are correctly initialized upto 8, but dev_priv
> should start out as zero, so presumably they will be zero.

Thanks, the warning should be fixed by commit

c6deb5e97ded ("drm/i915/pm: Make the wm parameter of print_wm_latency a pointer")

in drm-intel-next.

There doesn't actually seem to be a bug here, but I wonder if we should
send that to stable or v5.13-rc1+ anyway to stop people spending time on
the same issue.

BR,
Jani.

>
> Signed-off-by: Andi Kleen <andi@firstfloor.org>
> ---
>  drivers/gpu/drm/i915/i915_drv.h | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index cb62ddba2035..c80add5f6d33 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1095,11 +1095,11 @@ struct drm_i915_private {
>  		 * in 0.5us units for WM1+.
>  		 */
>  		/* primary */
> -		u16 pri_latency[5];
> +		u16 pri_latency[8];
>  		/* sprite */
> -		u16 spr_latency[5];
> +		u16 spr_latency[8];
>  		/* cursor */
> -		u16 cur_latency[5];
> +		u16 cur_latency[8];
>  		/*
>  		 * Raw watermark memory latency values
>  		 * for SKL for all 8 levels

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  parent reply	other threads:[~2021-05-05  6:33 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-05  3:37 [Intel-gfx] [PATCH] i915: Increase *_latency array size Andi Kleen
2021-05-05  4:23 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2021-05-05  5:43 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-05-05  6:32 ` Jani Nikula [this message]
2021-05-05 14:18   ` [Intel-gfx] [PATCH] " Andi Kleen
2021-05-05 14:25     ` Ville Syrjälä
2021-05-06 10:23       ` Jani Nikula

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