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From: Jani Nikula <jani.nikula@linux.intel.com>
To: Rodrigo Vivi <rodrigo.vivi@intel.com>,
	Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915/mtl: Add workarounds Wa_14017066071, Wa_14017654203
Date: Tue, 24 Jan 2023 10:58:05 +0200	[thread overview]
Message-ID: <87sfg071ia.fsf@intel.com> (raw)
In-Reply-To: <Y8pxOlXj3gk0I2Nz@intel.com>

On Fri, 20 Jan 2023, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> On Thu, Jan 19, 2023 at 05:06:38PM -0800, Radhakrishna Sripada wrote:
>> This patch add the workaround to disable Sampler-OOO to avoid hang
>> during a benchmark.
>> 
>> Original Author: Madhumitha Tolakanhalli Pradeep
>
> This is not how we handle this. We keep her original authorship email
> and signed-off.

Also, "This patch" is redundant, and once committed, just wrong.

>
>> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
>> ---
>>  drivers/gpu/drm/i915/gt/intel_gt_regs.h     | 1 +
>>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++++++
>>  2 files changed, 8 insertions(+)
>> 
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>> index 4a4bab261e66..27b06ff380a9 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>> @@ -1145,6 +1145,7 @@
>>  #define   ENABLE_SMALLPL			REG_BIT(15)
>>  #define   SC_DISABLE_POWER_OPTIMIZATION_EBB	REG_BIT(9)
>>  #define   GEN11_SAMPLER_ENABLE_HEADLESS_MSG	REG_BIT(5)
>> +#define   MTL_DISABLE_SAMPLER_SC_OOO		REG_BIT(3)
>>  
>>  #define GEN9_HALF_SLICE_CHICKEN7		MCR_REG(0xe194)
>>  #define   DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA	REG_BIT(15)
>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> index 918a271447e2..c52c5f9ad9ce 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> @@ -2332,6 +2332,13 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>>  		/* Wa_22014600077 */
>>  		wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
>>  				 ENABLE_EU_COUNT_FOR_TDL_FLUSH);
>> +
>> +		/*
>> +		 * Wa_14017066071: mtl-p/m[a0]
>> +		 * Wa_14017654203: mtl-p/m[a0]
>> +		 */
>> +		wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
>> +				 MTL_DISABLE_SAMPLER_SC_OOO);
>>  	}
>>  
>>  	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>> -- 
>> 2.34.1
>> 

-- 
Jani Nikula, Intel Open Source Graphics Center

  reply	other threads:[~2023-01-24  8:58 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-20  1:06 [Intel-gfx] [PATCH 1/2] drm/i915/mtl: Add workarounds Wa_14017066071, Wa_14017654203 Radhakrishna Sripada
2023-01-20  1:06 ` [Intel-gfx] [PATCH 2/2] drm/i915/mtl: Add Wa_22015279794 Radhakrishna Sripada
2023-01-20 10:47   ` Rodrigo Vivi
2023-01-20  1:21 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915/mtl: Add workarounds Wa_14017066071, Wa_14017654203 Patchwork
2023-01-20  1:35 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-01-20 10:47 ` [Intel-gfx] [PATCH 1/2] " Rodrigo Vivi
2023-01-24  8:58   ` Jani Nikula [this message]
2023-01-20 22:47 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] " Patchwork

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