Intel-GFX Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: "Dixit, Ashutosh" <ashutosh.dixit@intel.com>
To: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v4 04/16] drm/i915/perf: Determine gen12 oa ctx offset at runtime
Date: Wed, 12 Oct 2022 16:46:07 -0700	[thread overview]
Message-ID: <87sfjs8v28.wl-ashutosh.dixit@intel.com> (raw)
In-Reply-To: <20221012222739.27296-5-umesh.nerlige.ramappa@intel.com>

On Wed, 12 Oct 2022 15:27:27 -0700, Umesh Nerlige Ramappa wrote:
>
> +static u32 oa_context_image_offset(struct intel_context *ce, u32 reg)
> +{
> +	u32 offset, len = (ce->engine->context_size - PAGE_SIZE) / 4;
> +	u32 *state = ce->lrc_reg_state;
> +
> +	for (offset = 0; offset < len; ) {
> +		if (IS_MI_LRI_CMD(state[offset])) {
> +			/*
> +			 * We expect reg-value pairs in MI_LRI command, so
> +			 * MI_LRI_LEN() should be even, if not, issue a warning.
> +			 */
> +			drm_WARN_ON(&ce->engine->i915->drm,
> +				    MI_LRI_LEN(state[offset]) & 0x1);
> +
> +			if (oa_find_reg_in_lri(state, reg, &offset, len))
> +				break;
> +		} else {
> +			offset++;
> +		}
> +	}
> +
> +	/*
> +	 * Note that the the reg value is written to 'offset + 1' location, so
> +	 * ensure that the offset is less than (len - 1).
> +	 */
> +	return offset < len ? offset : U32_MAX;

Should this then be 'offset < len - 1'? It is actually equivalent since
length is even and we do idx += 2 in oa_find_reg_in_lri so 'offset < len'
is the same as 'offset < len - 1' but since we mention (len - 1) in the
comment maybe clearer to use 'offset < len - 1'?

  reply	other threads:[~2022-10-12 23:46 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-12 22:27 [Intel-gfx] [PATCH v4 00/16] Add DG2 OA support Umesh Nerlige Ramappa
2022-10-12 22:27 ` [Intel-gfx] [PATCH v4 01/16] drm/i915/perf: Fix OA filtering logic for GuC mode Umesh Nerlige Ramappa
2022-10-12 22:27 ` [Intel-gfx] [PATCH v4 02/16] drm/i915/perf: Add 32-bit OAG and OAR formats for DG2 Umesh Nerlige Ramappa
2022-10-12 22:27 ` [Intel-gfx] [PATCH v4 03/16] drm/i915/perf: Fix noa wait predication " Umesh Nerlige Ramappa
2022-10-12 22:27 ` [Intel-gfx] [PATCH v4 04/16] drm/i915/perf: Determine gen12 oa ctx offset at runtime Umesh Nerlige Ramappa
2022-10-12 23:46   ` Dixit, Ashutosh [this message]
2022-10-13 17:05     ` Umesh Nerlige Ramappa
2022-10-12 22:27 ` [Intel-gfx] [PATCH v4 05/16] drm/i915/perf: Enable bytes per clock reporting in OA Umesh Nerlige Ramappa
2022-10-12 22:27 ` [Intel-gfx] [PATCH v4 06/16] drm/i915/perf: Simply use stream->ctx Umesh Nerlige Ramappa
2022-10-12 22:27 ` [Intel-gfx] [PATCH v4 07/16] drm/i915/perf: Move gt-specific data from i915->perf to gt->perf Umesh Nerlige Ramappa
2022-10-12 22:27 ` [Intel-gfx] [PATCH v4 08/16] drm/i915/perf: Replace gt->perf.lock with stream->lock for file ops Umesh Nerlige Ramappa
2022-10-12 22:27 ` [Intel-gfx] [PATCH v4 09/16] drm/i915/perf: Use gt-specific ggtt for OA and noa-wait buffers Umesh Nerlige Ramappa
2022-10-12 22:27 ` [Intel-gfx] [PATCH v4 10/16] drm/i915/perf: Store a pointer to oa_format in oa_buffer Umesh Nerlige Ramappa
2022-10-12 22:27 ` [Intel-gfx] [PATCH v4 11/16] drm/i915/perf: Add Wa_1508761755:dg2 Umesh Nerlige Ramappa
2022-10-12 22:27 ` [Intel-gfx] [PATCH v4 12/16] drm/i915/perf: Apply Wa_18013179988 Umesh Nerlige Ramappa
2022-10-12 22:27 ` [Intel-gfx] [PATCH v4 13/16] drm/i915/perf: Save/restore EU flex counters across reset Umesh Nerlige Ramappa
2022-10-12 22:27 ` [Intel-gfx] [PATCH v4 14/16] drm/i915/guc: Support OA when Wa_16011777198 is enabled Umesh Nerlige Ramappa
2022-10-12 22:27 ` [Intel-gfx] [PATCH v4 15/16] drm/i915/perf: complete programming whitelisting for XEHPSDV Umesh Nerlige Ramappa
2022-10-12 22:27 ` [Intel-gfx] [PATCH v4 16/16] drm/i915/perf: Enable OA for DG2 Umesh Nerlige Ramappa
2022-10-12 22:54 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add DG2 OA support (rev6) Patchwork
2022-10-12 22:54 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-10-12 23:03 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-10-17 22:05 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Add DG2 OA support (rev7) Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=87sfjs8v28.wl-ashutosh.dixit@intel.com \
    --to=ashutosh.dixit@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=umesh.nerlige.ramappa@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox