From: Jani Nikula <jani.nikula@linux.intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v2 05/18] drm/i915: Reorder 12.4 lut udw vs. ldw functions
Date: Fri, 11 Nov 2022 17:15:56 +0200 [thread overview]
Message-ID: <87tu354j4j.fsf@intel.com> (raw)
In-Reply-To: <20221110082144.19666-6-ville.syrjala@linux.intel.com>
On Thu, 10 Nov 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Satisfy my ocd and define ilk_lut_12p4_ldw() before ilk_lut_12p4_udw().
> That is the order all the other similar functions use.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 16 ++++++++--------
> 1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index 8e92eb61abac..9c259e144772 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -482,14 +482,6 @@ static void ilk_lut_10_pack(struct drm_color_lut *entry, u32 val)
> entry->blue = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_10_BLUE_MASK, val), 10);
> }
>
> -/* ilk+ "12.4" interpolated format (high 10 bits) */
> -static u32 ilk_lut_12p4_udw(const struct drm_color_lut *color)
> -{
> - return REG_FIELD_PREP(PREC_PALETTE_12P4_RED_UDW_MASK, color->red >> 6) |
> - REG_FIELD_PREP(PREC_PALETTE_12P4_GREEN_UDW_MASK, color->green >> 6) |
> - REG_FIELD_PREP(PREC_PALETTE_12P4_BLUE_UDW_MASK, color->blue >> 6);
> -}
> -
> /* ilk+ "12.4" interpolated format (low 6 bits) */
> static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color)
> {
> @@ -498,6 +490,14 @@ static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color)
> REG_FIELD_PREP(PREC_PALETTE_12P4_BLUE_LDW_MASK, color->blue & 0x3f);
> }
>
> +/* ilk+ "12.4" interpolated format (high 10 bits) */
> +static u32 ilk_lut_12p4_udw(const struct drm_color_lut *color)
> +{
> + return REG_FIELD_PREP(PREC_PALETTE_12P4_RED_UDW_MASK, color->red >> 6) |
> + REG_FIELD_PREP(PREC_PALETTE_12P4_GREEN_UDW_MASK, color->green >> 6) |
> + REG_FIELD_PREP(PREC_PALETTE_12P4_BLUE_UDW_MASK, color->blue >> 6);
> +}
> +
> static void ilk_lut_12p4_pack(struct drm_color_lut *entry, u32 ldw, u32 udw)
> {
> entry->red = REG_FIELD_GET(PREC_PALETTE_12P4_RED_UDW_MASK, udw) << 6 |
--
Jani Nikula, Intel Open Source Graphics Center
next prev parent reply other threads:[~2022-11-11 15:16 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-10 8:21 [Intel-gfx] [PATCH v2 00/18] drm/i915: Finish (de)gamma readout Ville Syrjala
2022-11-10 8:21 ` [Intel-gfx] [PATCH v2 01/18] drm/i915: Clean up legacy palette defines Ville Syrjala
2022-11-11 15:09 ` Jani Nikula
2022-11-11 18:24 ` Ville Syrjälä
2022-11-10 8:21 ` [Intel-gfx] [PATCH v2 02/18] drm/i915: Clean up 10bit precision " Ville Syrjala
2022-11-11 15:10 ` Jani Nikula
2022-11-10 8:21 ` [Intel-gfx] [PATCH v2 03/18] drm/i915: Clean up 12.4bit " Ville Syrjala
2022-11-11 15:13 ` Jani Nikula
2022-11-10 8:21 ` [Intel-gfx] [PATCH v2 04/18] drm/i915: Clean up chv CGM (de)gamma defines Ville Syrjala
2022-11-11 15:15 ` Jani Nikula
2022-11-10 8:21 ` [Intel-gfx] [PATCH v2 05/18] drm/i915: Reorder 12.4 lut udw vs. ldw functions Ville Syrjala
2022-11-11 15:15 ` Jani Nikula [this message]
2022-11-10 8:21 ` [Intel-gfx] [PATCH v2 06/18] drm/i915: Fix adl+ degamma LUT size Ville Syrjala
2022-11-10 8:21 ` [Intel-gfx] [PATCH v2 07/18] drm/i915: Add glk+ degamma readout Ville Syrjala
2022-11-10 8:21 ` [Intel-gfx] [PATCH v2 08/18] drm/i915: Read out CHV CGM degamma Ville Syrjala
2022-11-10 8:21 ` [Intel-gfx] [PATCH v2 09/18] drm/i915: Add gamma/degamma readout for bdw+ Ville Syrjala
2022-11-10 8:21 ` [Intel-gfx] [PATCH v2 10/18] drm/i915: Add gamma/degamma readout for ivb/hsw Ville Syrjala
2022-11-10 8:21 ` [Intel-gfx] [PATCH v2 11/18] drm/i915: Make ilk_read_luts() capable of degamma readout Ville Syrjala
2022-11-10 8:21 ` [Intel-gfx] [PATCH v2 12/18] drm/i915: Make .read_luts() mandatory Ville Syrjala
2022-11-10 8:21 ` [Intel-gfx] [PATCH v2 13/18] drm/i915: Finish the LUT state checker Ville Syrjala
2022-11-12 15:55 ` [Intel-gfx] [PATCH v3 " Ville Syrjala
2022-11-10 8:21 ` [Intel-gfx] [PATCH v2 14/18] drm/i915: Rework legacy LUT handling Ville Syrjala
2022-11-10 8:21 ` [Intel-gfx] [PATCH v2 15/18] drm/i915: Use hw degamma LUT for sw gamma on glk with YCbCr output Ville Syrjala
2022-11-10 8:21 ` [Intel-gfx] [PATCH v2 16/18] drm/i915: Use gamma LUT for RGB limited range compression Ville Syrjala
2022-11-10 8:21 ` [Intel-gfx] [PATCH v2 17/18] drm/i915: Add 10bit gamma mode for gen2/3 Ville Syrjala
2022-11-12 15:56 ` [Intel-gfx] [PATCH v3 " Ville Syrjala
2022-11-10 8:21 ` [Intel-gfx] [PATCH v2 18/18] drm/i915: Do state check for color management changes Ville Syrjala
2022-11-11 14:37 ` [Intel-gfx] [PATCH v3 " Ville Syrjala
2022-11-10 21:55 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Finish (de)gamma readout (rev2) Patchwork
2022-11-10 21:55 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-11-10 22:17 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-11-11 14:59 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Finish (de)gamma readout (rev3) Patchwork
2022-11-11 15:24 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-11-11 19:27 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Finish (de)gamma readout (rev4) Patchwork
2022-11-11 19:27 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-11-11 19:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-11-12 12:47 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-11-12 16:37 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Finish (de)gamma readout (rev6) Patchwork
2022-11-12 16:37 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-11-12 16:59 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-11-12 19:47 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Finish (de)gamma readout (rev7) Patchwork
2022-11-12 19:47 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-11-12 20:09 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-11-12 21:49 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=87tu354j4j.fsf@intel.com \
--to=jani.nikula@linux.intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=ville.syrjala@linux.intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox