Re: [PATCH 04/22] drm/i915/icl: WaL3BankAddressHashing

[Mika Kuoppala <mika.kuoppala@linux.intel.com>]

Oscar Mateo <oscar.mateo@intel.com> writes:

> Revert to an L3 non-hash model, for performance reasons.
>
> v2:
>   - Place the WA name above the actual change
>   - Improve the register naming
> v3:
>   - Rebased
>   - Renamed to Wa_1604223664
> v4: Rebased on top of the WA refactoring
>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h          |  6 ++++++
>  drivers/gpu/drm/i915/intel_workarounds.c | 20 ++++++++++++++++----
>  2 files changed, 22 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a6b1f85..5637cd7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8218,6 +8218,12 @@ enum {
>  #define GEN8_GARBCNTL				_MMIO(0xB004)
>  #define   GEN9_GAPS_TSV_CREDIT_DISABLE		(1 << 7)
>  #define   GEN11_ARBITRATION_PRIO_ORDER_MASK	(0x3f << 22)
> +#define   GEN11_HASH_CTRL_EXCL_MASK		(0x7f << 0)
> +#define   GEN11_HASH_CTRL_EXCL_BIT0		(1 << 0)
> +
> +#define GEN11_GLBLINVL				_MMIO(0xB404)
> +#define   GEN11_BANK_HASH_ADDR_EXCL_BIT0	(1 << 0)

(1 << 5)

> +#define   GEN11_BANK_HASH_ADDR_EXCL_MASK	(0x3f << 5)

0x7f
-Mika

>  
>  #define GEN10_DFR_RATIO_EN_AND_CHICKEN	_MMIO(0x9550)
>  #define   DFR_DISABLE			(1 << 9)
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index ffd27a1..83a53cc 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -704,11 +704,23 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>  	I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
>  				    GEN8_LQSC_FLUSH_COHERENT_LINES));
>  
> -	/* Wa_1405543622:icl
> -	 * Formerly known as WaGAPZPriorityScheme
> +	I915_WRITE(GEN8_GARBCNTL,
> +		   /* Wa_1604223664:icl
> +		    * Formerly known as WaL3BankAddressHashing
> +		    */
> +		   ((I915_READ(GEN8_GARBCNTL) & ~GEN11_HASH_CTRL_EXCL_MASK) |
> +		    GEN11_HASH_CTRL_EXCL_BIT0 |
> +		    /* Wa_1405543622:icl
> +		     * Formerly known as WaGAPZPriorityScheme
> +		     */
> +		    GEN11_ARBITRATION_PRIO_ORDER_MASK));
> +
> +	/* Wa_1604223664:icl
> +	 * Formerly known as WaL3BankAddressHashing
>  	 */
> -	I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
> -				   GEN11_ARBITRATION_PRIO_ORDER_MASK));
> +	I915_WRITE(GEN11_GLBLINVL,
> +		   ((I915_READ(GEN11_GLBLINVL) & ~GEN11_BANK_HASH_ADDR_EXCL_MASK) |
> +		    GEN11_BANK_HASH_ADDR_EXCL_BIT0));
>  }
>  
>  void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> -- 
> 1.9.1
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