Re: [Intel-gfx] [PATCH v7 3/3] drm/i915/icl: whitelist PS_(DEPTH|INVOCATION)_COUNT

[Mika Kuoppala <mika.kuoppala@linux.intel.com>]

Lionel Landwerlin <lionel.g.landwerlin@intel.com> writes:

> The same tests failing on CFL+ platforms are also failing on ICL.
> Documentation doesn't list the
> WaAllowPMDepthAndInvocationCountAccessFromUMD workaround for ICL but
> applying it fixes the same tests as CFL.

Didn't find more documentation either but I have asked
for the wa author for update.

>
> v2: Use only one whitelist entry (Lionel)
>
> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> Tested-by:  Anuj Phogat <anuj.phogat@gmail.com>
> Cc: stable@vger.kernel.org

The register offsets are the same so we can't really do
harm with this so we go with the evidence,

Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index b117583e38bb..a908d829d6bd 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1138,6 +1138,19 @@ static void icl_whitelist_build(struct intel_engine_cs *engine)
>  
>  		/* WaEnableStateCacheRedirectToCS:icl */
>  		whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1);
> +
> +		/*
> +		 * WaAllowPMDepthAndInvocationCountAccessFromUMD:icl
> +		 *
> +		 * This covers 4 register which are next to one another :
> +		 *   - PS_INVOCATION_COUNT
> +		 *   - PS_INVOCATION_COUNT_UDW
> +		 *   - PS_DEPTH_COUNT
> +		 *   - PS_DEPTH_COUNT_UDW
> +		 */
> +		whitelist_reg_ext(w, PS_INVOCATION_COUNT,
> +				  RING_FORCE_TO_NONPRIV_RD |
> +				  RING_FORCE_TO_NONPRIV_RANGE_4);
>  		break;
>  
>  	case VIDEO_DECODE_CLASS:
> -- 
> 2.21.0.392.gf8f6787159e
>
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