From: Jani Nikula <jani.nikula@intel.com>
To: Shobhit Kumar <shobhit.kumar@intel.com>, intel-gfx@lists.freedesktop.org
Cc: vijayakumar.balakrishnan@intel.com, yogesh.mohan.marimuthu@intel.com
Subject: Re: [PATCH v3 4/7] drm/i915: Try harder to get best m, n, p values with minimal error
Date: Wed, 11 Dec 2013 11:21:40 +0200 [thread overview]
Message-ID: <87wqjb68uz.fsf@intel.com> (raw)
In-Reply-To: <1386657900-12132-5-git-send-email-shobhit.kumar@intel.com>
On Tue, 10 Dec 2013, Shobhit Kumar <shobhit.kumar@intel.com> wrote:
> Basically check for both +ive and -ive deviation from target clock and
> pick the one with minimal error. If we get a direct match, break from
> loop to acheive some optimization.
>
> v2: Use signed variable for target and calculated dsi clock values
>
I think this could be simplified still, but that's bikeshedding...
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Vijayakumar Balakrishnan <vijayakumar.balakrishnan@intel.com>
> Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dsi_pll.c | 30 ++++++++++++++++++++----------
> 1 file changed, 20 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index 0d1b17f..ba79ec1 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -169,8 +169,8 @@ static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp)
> u32 ref_clk;
> u32 error;
> u32 tmp_error;
> - u32 target_dsi_clk;
> - u32 calc_dsi_clk;
> + int target_dsi_clk;
> + int calc_dsi_clk;
> u32 calc_m;
> u32 calc_p;
> u32 m_seed;
> @@ -184,22 +184,32 @@ static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp)
> ref_clk = 25000;
> target_dsi_clk = dsi_clk;
> error = 0xFFFFFFFF;
> + tmp_error = 0xFFFFFFFF;
> calc_m = 0;
> calc_p = 0;
>
> for (m = 62; m <= 92; m++) {
> for (p = 2; p <= 6; p++) {
> -
> + /* Find the optimal m and p divisors
> + with minimal error +/- the required clock */
> calc_dsi_clk = (m * ref_clk) / p;
> - if (calc_dsi_clk >= target_dsi_clk) {
> - tmp_error = calc_dsi_clk - target_dsi_clk;
> - if (tmp_error < error) {
> - error = tmp_error;
> - calc_m = m;
> - calc_p = p;
> - }
> + if (calc_dsi_clk == target_dsi_clk) {
> + calc_m = m;
> + calc_p = p;
> + error = 0;
> + break;
> + } else
> + tmp_error = abs(target_dsi_clk - calc_dsi_clk);
> +
> + if (tmp_error < error) {
> + error = tmp_error;
> + calc_m = m;
> + calc_p = p;
> }
> }
> +
> + if (error == 0)
> + break;
> }
>
> m_seed = lfsr_converts[calc_m - 62];
> --
> 1.8.3.2
>
--
Jani Nikula, Intel Open Source Technology Center
next prev parent reply other threads:[~2013-12-11 9:19 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-10 6:44 [PATCH v3 0/7] drm/i915: Baytrail MIPI DSI support Updated Shobhit Kumar
2013-12-10 6:44 ` [PATCH v3 1/7] drm/i915: Add more dev ops for MIPI sub encoder Shobhit Kumar
2013-12-11 9:20 ` Jani Nikula
2013-12-10 6:44 ` [PATCH v3 2/7] drm/i915: Use FLISDSI interface for band gap reset Shobhit Kumar
2013-12-10 6:44 ` [PATCH v3 3/7] drm/i915: Compute dsi_clk from pixel clock Shobhit Kumar
2013-12-10 6:44 ` [PATCH v3 4/7] drm/i915: Try harder to get best m, n, p values with minimal error Shobhit Kumar
2013-12-11 9:21 ` Jani Nikula [this message]
2013-12-10 6:44 ` [PATCH v3 5/7] drm/i915: Reorganize the DSI enable/disable sequence Shobhit Kumar
2013-12-11 11:02 ` Jani Nikula
2013-12-11 12:18 ` Shobhit Kumar
2013-12-10 6:44 ` [PATCH v3 6/7] drm/i915: Remove redundant DSI PLL enabling Shobhit Kumar
2013-12-10 6:45 ` [PATCH v3 7/7] drm/i915: Parametrize the dphy and other spec specific parameters Shobhit Kumar
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