From: Jani Nikula <jani.nikula@linux.intel.com>
To: "Lisovskiy, Stanislav" <stanislav.lisovskiy@intel.com>,
Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [1/2] drm/display/dp: Assume 8 bpc support when DSC is supported
Date: Wed, 30 Aug 2023 15:00:56 +0300 [thread overview]
Message-ID: <87zg28zqmf.fsf@intel.com> (raw)
In-Reply-To: <ZO71Dbu1NvY8qYup@intel.com>
On Wed, 30 Aug 2023, "Lisovskiy, Stanislav" <stanislav.lisovskiy@intel.com> wrote:
> On Thu, Aug 24, 2023 at 06:21:20PM +0530, Ankit Nautiyal wrote:
>> As per DP v1.4, a DP DSC Sink device shall support 8bpc in DPCD 6Ah.
>> Apparently some panels that do support DSC, are not setting the bit for
>> 8bpc.
>>
>> So always assume 8bpc support by DSC decoder, when DSC is claimed to be
>> supported.
>>
>> v2: Use helper to get check dsc support. (Ankit)
>> v3: Fix styling and other typos. (Jani)
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>
> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Pushed both to drm-intel-next, with Maxime's ack, thanks for the patches
and review.
BR,
Jani.
>
>> ---
>> drivers/gpu/drm/display/drm_dp_helper.c | 8 ++++++--
>> 1 file changed, 6 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
>> index e6a78fd32380..8a1b64c57dfd 100644
>> --- a/drivers/gpu/drm/display/drm_dp_helper.c
>> +++ b/drivers/gpu/drm/display/drm_dp_helper.c
>> @@ -2449,12 +2449,16 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S
>> int num_bpc = 0;
>> u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT];
>>
>> + if (!drm_dp_sink_supports_dsc(dsc_dpcd))
>> + return 0;
>> +
>> if (color_depth & DP_DSC_12_BPC)
>> dsc_bpc[num_bpc++] = 12;
>> if (color_depth & DP_DSC_10_BPC)
>> dsc_bpc[num_bpc++] = 10;
>> - if (color_depth & DP_DSC_8_BPC)
>> - dsc_bpc[num_bpc++] = 8;
>> +
>> + /* A DP DSC Sink device shall support 8 bpc. */
>> + dsc_bpc[num_bpc++] = 8;
>>
>> return num_bpc;
>> }
--
Jani Nikula, Intel Open Source Graphics Center
next prev parent reply other threads:[~2023-08-30 12:01 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-24 12:51 [Intel-gfx] [PATCH 0/2] eDP DSC fixes Ankit Nautiyal
2023-08-24 12:51 ` [Intel-gfx] [PATCH 1/2] drm/display/dp: Assume 8 bpc support when DSC is supported Ankit Nautiyal
2023-08-29 8:44 ` Jani Nikula
2023-08-29 9:01 ` Maxime Ripard
2023-08-30 7:51 ` [Intel-gfx] [1/2] " Lisovskiy, Stanislav
2023-08-30 12:00 ` Jani Nikula [this message]
2023-08-24 12:51 ` [Intel-gfx] [PATCH 2/2] drivers/drm/i915: Honor limits->max_bpp while computing DSC max input bpp Ankit Nautiyal
2023-08-30 12:02 ` Jani Nikula
2023-08-24 14:25 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for eDP DSC fixes (rev3) Patchwork
2023-08-24 14:25 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-08-24 14:38 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-08-25 1:06 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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