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From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915/execlists: Record the active CCID from before reset
Date: Thu, 02 Apr 2020 23:18:26 +0300	[thread overview]
Message-ID: <87zhbtod4d.fsf@gaia.fi.intel.com> (raw)
In-Reply-To: <20200401110435.30389-2-chris@chris-wilson.co.uk>

Chris Wilson <chris@chris-wilson.co.uk> writes:

> If we cannot trust the reset will flush out the CS event queue such that
> process_csb() reports an accurate view of HW, we will need to search the
> active and pending contexts to determine which was actually running at
> the time we issued the reset.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/gt/intel_engine_types.h | 5 +++++
>  drivers/gpu/drm/i915/gt/intel_lrc.c          | 4 +++-
>  2 files changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> index 80cdde712842..4804587442e7 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> @@ -166,6 +166,11 @@ struct intel_engine_execlists {
>  	 */
>  	u32 error_interrupt;
>  
> +	/**
> +	 * @reset_ccid: Active CCID [EXECLISTS_STATUS_HI] at the time of reset
> +	 */
> +	u32 reset_ccid;
> +
>  	/**
>  	 * @no_priolist: priority lists disabled
>  	 */
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index f028114714cd..55bf3cdf3b38 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -3724,6 +3724,8 @@ static void execlists_reset_prepare(struct intel_engine_cs *engine)
>  	 */
>  	ring_set_paused(engine, 1);
>  	intel_engine_stop_cs(engine);
> +
> +	engine->execlists.reset_ccid = active_ccid(engine);
>  }
>  
>  static void reset_csb_pointers(struct intel_engine_cs *engine)
> @@ -3798,7 +3800,7 @@ static void __execlists_reset(struct intel_engine_cs *engine, bool stalled)
>  	 * its request, it was still running at the time of the
>  	 * reset and will have been clobbered.
>  	 */
> -	rq = execlists_active(execlists);
> +	rq = active_context(engine, engine->execlists.reset_ccid);
>  	if (!rq)
>  		goto unwind;
>  
> -- 
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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  reply	other threads:[~2020-04-02 20:20 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-01 11:04 [Intel-gfx] [PATCH 1/2] drm/i915/execlists: Peek at the next submission for error interrupts Chris Wilson
2020-04-01 11:04 ` [Intel-gfx] [PATCH 2/2] drm/i915/execlists: Record the active CCID from before reset Chris Wilson
2020-04-02 20:18   ` Mika Kuoppala [this message]
2020-04-01 11:37 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/execlists: Peek at the next submission for error interrupts Patchwork
2020-04-02  8:41 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-04-02 20:16 ` [Intel-gfx] [PATCH 1/2] " Mika Kuoppala
2020-04-02 20:30   ` Chris Wilson

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