From: Jani Nikula <jani.nikula@intel.com>
To: Vandita Kulkarni <vandita.kulkarni@intel.com>,
intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/3] drm/i915: Fix pipe config mismatch for bpp, output format
Date: Wed, 17 Apr 2019 14:23:46 +0300 [thread overview]
Message-ID: <87zhoovprx.fsf@intel.com> (raw)
In-Reply-To: <1554365187-30575-3-git-send-email-vandita.kulkarni@intel.com>
On Thu, 04 Apr 2019, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote:
> Read back the pixel fomrat register and get the bpp.
>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> ---
> drivers/gpu/drm/i915/icl_dsi.c | 28 ++++++++++++++++++++++++++++
> 1 file changed, 28 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index db6bc3d..69cd6b2 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -1226,6 +1226,30 @@ static void gen11_dsi_get_timings(struct intel_encoder *encoder,
> adjusted_mode->crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
> }
>
> +enum mipi_dsi_pixel_format
> +gen11_dsi_get_pixel_fmt(struct drm_i915_private *dev_priv,
> + struct intel_crtc_state *pipe_config)
> +{
> + u32 tmp;
> + /* get config for dsi0 transcoder only */
> + enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
> +
> + tmp = I915_READ(DSI_TRANS_FUNC_CONF(cpu_transcoder));
> + tmp &= PIX_FMT_MASK;
> +
> + switch (tmp) {
> + default:
> + case PIX_FMT_RGB565:
> + return MIPI_DSI_FMT_RGB565;
> + case PIX_FMT_RGB666_PACKED:
> + return MIPI_DSI_FMT_RGB666_PACKED;
> + case PIX_FMT_RGB666_LOOSE:
> + return MIPI_DSI_FMT_RGB666;
> + case PIX_FMT_RGB888:
> + return MIPI_DSI_FMT_RGB888;
> + }
> +}
> +
> static void gen11_dsi_get_config(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config)
> {
> @@ -1238,6 +1262,9 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
> pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk;
> gen11_dsi_get_timings(encoder, pipe_config);
> pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
> + pipe_config->pipe_bpp = mipi_dsi_pixel_format_to_bpp
> + (gen11_dsi_get_pixel_fmt(dev_priv,
> + pipe_config));
Please see how this is done for VLV DSI. It now uses PIPEMISC for
this. I'd like the two to be the same.
BR,
Jani.
> }
>
> static int gen11_dsi_compute_config(struct intel_encoder *encoder,
> @@ -1253,6 +1280,7 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
> struct drm_display_mode *adjusted_mode =
> &pipe_config->base.adjusted_mode;
>
> + pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
> intel_fixed_panel_mode(fixed_mode, adjusted_mode);
> intel_pch_panel_fitting(crtc, pipe_config, conn_state->scaling_mode);
--
Jani Nikula, Intel Open Source Graphics Center
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next prev parent reply other threads:[~2019-04-17 11:21 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-04 8:06 [PATCH 0/3] Fix mipi dsi pipe_config mismatch for icl Vandita Kulkarni
2019-04-04 8:06 ` [PATCH 1/3] drm/i915: Fix pipe config timing mismatch warnings Vandita Kulkarni
2019-04-04 20:29 ` Ville Syrjälä
2019-04-05 8:25 ` Kulkarni, Vandita
2019-04-17 11:16 ` Jani Nikula
2019-04-04 8:06 ` [PATCH 2/3] drm/i915: Fix pipe config mismatch for bpp, output format Vandita Kulkarni
2019-04-04 14:06 ` kbuild test robot
2019-04-04 14:06 ` [RFC PATCH] drm/i915: gen11_dsi_get_pixel_fmt can be static kbuild test robot
2019-04-17 11:23 ` Jani Nikula [this message]
2019-04-04 8:06 ` [PATCH 3/3] drm/i915: Fix pixel clock and crtc clock config mismatch Vandita Kulkarni
2019-04-17 13:42 ` Jani Nikula
2019-04-04 18:13 ` ✗ Fi.CI.BAT: failure for Fix mipi dsi pipe_config mismatch for icl (rev2) Patchwork
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