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From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 3/8] drm/i915/ringbuffer: Clear semaphore sync registers on ring init
Date: Mon, 03 Dec 2018 14:05:25 +0200	[thread overview]
Message-ID: <87zhtmery2.fsf@gaia.fi.intel.com> (raw)
In-Reply-To: <20181203113701.12106-3-chris@chris-wilson.co.uk>

Chris Wilson <chris@chris-wilson.co.uk> writes:

> Ensure that the sync registers are cleared every time we restart the
> ring to avoid stale values from creeping in from random neutrinos.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++++++
>  1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 992889f9e0ff..81b10d85b738 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -529,6 +529,13 @@ static int init_ring_common(struct intel_engine_cs *engine)
>  
>  	intel_engine_reset_breadcrumbs(engine);
>  
> +	if (HAS_LEGACY_SEMAPHORES(engine->i915)) {
> +		I915_WRITE(RING_SYNC_0(engine->mmio_base), 0);
> +		I915_WRITE(RING_SYNC_1(engine->mmio_base), 0);
> +		if (HAS_VEBOX(dev_priv))

Minor nitpick: mixed i915 and dev_priv usage. 

Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

> +			I915_WRITE(RING_SYNC_2(engine->mmio_base), 0);
> +	}
> +
>  	/* Enforce ordering by reading HEAD register back */
>  	I915_READ_HEAD(engine);
>  
> -- 
> 2.20.0.rc1
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  reply	other threads:[~2018-12-03 12:06 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-12-03 11:36 [PATCH 1/8] drm/i915/breadcrumbs: Reduce missed-breadcrumb false positive rate Chris Wilson
2018-12-03 11:36 ` [PATCH 2/8] drm/i915: Complete the fences as they are cancelled due to wedging Chris Wilson
2018-12-03 17:11   ` Tvrtko Ursulin
2018-12-03 17:36     ` Chris Wilson
2018-12-04 10:30       ` Tvrtko Ursulin
2018-12-03 11:36 ` [PATCH 3/8] drm/i915/ringbuffer: Clear semaphore sync registers on ring init Chris Wilson
2018-12-03 12:05   ` Mika Kuoppala [this message]
2018-12-03 12:15     ` Chris Wilson
2018-12-03 11:36 ` [PATCH 4/8] drm/i915: Allocate a common scratch page Chris Wilson
2018-12-03 15:28   ` Mika Kuoppala
2018-12-03 17:10     ` Chris Wilson
2018-12-03 17:29   ` [PATCH v2] " Chris Wilson
2018-12-03 11:36 ` [PATCH 5/8] drm/i915: Flush GPU relocs harder for gen3 Chris Wilson
2018-12-03 11:36 ` [PATCH 6/8] drm/i915/selftests: Terminate hangcheck sanitycheck forcibly Chris Wilson
2018-12-03 12:09   ` Mika Kuoppala
2018-12-03 12:17     ` Chris Wilson
2018-12-03 12:21       ` Mika Kuoppala
2018-12-03 11:37 ` [PATCH 7/8] drm/i915/selftests: Reorder request allocation vs vma pinning Chris Wilson
2018-12-04 11:06   ` Tvrtko Ursulin
2018-12-03 11:37 ` [PATCH 8/8] drm/i915: Pipeline PDP updates for Braswell Chris Wilson
2018-12-04 11:53   ` Tvrtko Ursulin
2018-12-04 12:09     ` Chris Wilson
2018-12-03 12:00 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/8] drm/i915/breadcrumbs: Reduce missed-breadcrumb false positive rate Patchwork
2018-12-03 12:03 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-12-03 12:17 ` ✓ Fi.CI.BAT: success " Patchwork
2018-12-03 13:49 ` [PATCH 1/8] " Tvrtko Ursulin
2018-12-03 15:01 ` ✓ Fi.CI.IGT: success for series starting with [1/8] " Patchwork
2018-12-03 17:42 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/8] drm/i915/breadcrumbs: Reduce missed-breadcrumb false positive rate (rev2) Patchwork
2018-12-03 17:44 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-12-04  8:40 ` ✓ Fi.CI.BAT: success " Patchwork
2018-12-04 11:22 ` ✓ Fi.CI.IGT: " Patchwork

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