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From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 3/7] drm/i915/execlists: Move the reset bits to a more natural home
Date: Mon, 05 Feb 2018 17:19:19 +0200	[thread overview]
Message-ID: <87zi4ntqfc.fsf@gaia.fi.intel.com> (raw)
In-Reply-To: <20180205092201.19476-3-chris@chris-wilson.co.uk>

Chris Wilson <chris@chris-wilson.co.uk> writes:

> In preparation for the next patch, we want the engine to appear idle
> after a reset (if there are no requests in flight). For execlists, this
> entails clearing the active status on reset, it will be regenerated on
> restarting the engine after the reset. In the process, note that a
> couple of other status flags and checks could be moved into the
> describing function.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_lrc.c | 13 ++++++++-----
>  1 file changed, 8 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index deeedfc9fe44..0af9488e4070 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1462,6 +1462,9 @@ static void enable_execlists(struct intel_engine_cs *engine)
>  	I915_WRITE(RING_HWS_PGA(engine->mmio_base),
>  		   engine->status_page.ggtt_offset);
>  	POSTING_READ(RING_HWS_PGA(engine->mmio_base));
> +
> +	/* Following the reset, we need to reload the CSB read/write pointers */
> +	engine->execlists.csb_head = -1;
>  }
>  
>  static int gen8_init_common_ring(struct intel_engine_cs *engine)
> @@ -1479,11 +1482,6 @@ static int gen8_init_common_ring(struct intel_engine_cs *engine)
>  	enable_execlists(engine);
>  	DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name);
>  
> -	GEM_BUG_ON(engine->id >= ARRAY_SIZE(gtiir));
> -
> -	execlists->csb_head = -1;
> -	execlists->active = 0;
> -
>  	/* After a GPU reset, we may have requests to replay */
>  	if (execlists->first)
>  		tasklet_schedule(&execlists->tasklet);
> @@ -1529,6 +1527,8 @@ static void reset_irq(struct intel_engine_cs *engine)
>  	struct drm_i915_private *dev_priv = engine->i915;
>  	int i;
>  
> +	GEM_BUG_ON(engine->id >= ARRAY_SIZE(gtiir));
> +
>  	/*
>  	 * Clear any pending interrupt state.
>  	 *
> @@ -1577,6 +1577,9 @@ static void reset_common_ring(struct intel_engine_cs *engine,
>  
>  	spin_unlock_irqrestore(&engine->timeline->lock, flags);
>  
> +	/* Mark all CS interrupts as complete */
> +	execlists->active = 0;
> +
>  	/* If the request was innocent, we leave the request in the ELSP
>  	 * and will try to replay it on restarting. The context image may
>  	 * have been corrupted by the reset, in which case we may have
> -- 
> 2.15.1
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  reply	other threads:[~2018-02-05 15:20 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-02-05  9:21 [PATCH 1/7] drm/i915/selftests: Flush old resets between engines Chris Wilson
2018-02-05  9:21 ` [PATCH 2/7] drm/i915/selftests: Use a sacrificial context for hang testing Chris Wilson
2018-02-05 14:02   ` Mika Kuoppala
2018-02-05 14:06     ` Chris Wilson
2018-02-05  9:21 ` [PATCH 3/7] drm/i915/execlists: Move the reset bits to a more natural home Chris Wilson
2018-02-05 15:19   ` Mika Kuoppala [this message]
2018-02-05  9:21 ` [PATCH 4/7] drm/i915: Skip post-reset request emission if the engine is not idle Chris Wilson
2018-02-05  9:21 ` [PATCH 5/7] drm/i915: Show the GPU state when declaring wedged Chris Wilson
2018-02-05  9:51   ` Mika Kuoppala
2018-02-05 10:02     ` Chris Wilson
2018-02-05  9:22 ` [PATCH 6/7] drm/i915/execlists: Remove the startup spam Chris Wilson
2018-02-05  9:22 ` [PATCH 7/7] drm/i915: Remove unbannable context spam from reset Chris Wilson
2018-02-05  9:30   ` Chris Wilson
2018-02-05 13:27     ` Chris Wilson
2018-02-05  9:58 ` ✗ Fi.CI.BAT: warning for series starting with [1/7] drm/i915/selftests: Flush old resets between engines Patchwork
2018-02-05 14:27 ` [PATCH 1/7] " Mika Kuoppala

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