From: Jani Nikula <jani.nikula@linux.intel.com>
To: Luca Coelho <luciano.coelho@intel.com>, intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org
Subject: Re: [PATCH v2 1/4] drm/i915/display: harden masks in HSW_AUD_PIN_ELD_CP_VLD macros
Date: Fri, 29 May 2026 19:32:33 +0300 [thread overview]
Message-ID: <8efc55da36b1c67e774ff5ea2da66a1cb6030774@intel.com> (raw)
In-Reply-To: <20260528093222.2758007-2-luciano.coelho@intel.com>
On Thu, 28 May 2026, Luca Coelho <luciano.coelho@intel.com> wrote:
> HSW_AUD_PIN_ELD_CP_VLD has a 4-bit field per transcoder for
> TRANSCODER_A..TRANSCODER_D only (bits 0..15). Any other transcoder
> value (TRANSCODER_EDP, TRANSCODER_DSI_*, INVALID_TRANSCODER) is not
> valid here.
>
> This is not a problem with the current implementation, because trans
> is always valid when these macros are called, but it's more robust to
> mask the index to the low 2 bits so the shift is always well-defined.
>
> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_audio_regs.h | 16 ++++++++++++----
> 1 file changed, 12 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_audio_regs.h b/drivers/gpu/drm/i915/display/intel_audio_regs.h
> index 4c31844d21df..03e2dedf2714 100644
> --- a/drivers/gpu/drm/i915/display/intel_audio_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_audio_regs.h
> @@ -109,12 +109,20 @@
> #define _HSW_AUD_EDID_DATA_B 0x65150
> #define HSW_AUD_EDID_DATA(trans) _MMIO_TRANS(trans, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B)
>
> +/*
> + * HSW_AUD_PIN_ELD_CP_VLD has a 4-bit field per transcoder for
> + * TRANSCODER_A..TRANSCODER_D only (bits 0..15). Any other transcoder
> + * value (TRANSCODER_EDP, TRANSCODER_DSI_*, INVALID_TRANSCODER) is not
> + * valid here. Mask the index to the low 2 bits so the shift is
> + * always well-defined.
> + */
> #define HSW_AUD_PIPE_CONV_CFG _MMIO(0x6507c)
> #define HSW_AUD_PIN_ELD_CP_VLD _MMIO(0x650c0)
> -#define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4))
> -#define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4))
> -#define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4))
> -#define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4))
> +#define __AUDIO_TRANS_SHIFT(trans) (((trans) & 0x3) * 4)
> +#define AUDIO_INACTIVE(trans) REG_BIT(__AUDIO_TRANS_SHIFT(trans) + 3)
> +#define AUDIO_OUTPUT_ENABLE(trans) REG_BIT(__AUDIO_TRANS_SHIFT(trans) + 2)
> +#define AUDIO_CP_READY(trans) REG_BIT(__AUDIO_TRANS_SHIFT(trans) + 1)
> +#define AUDIO_ELD_VALID(trans) REG_BIT(__AUDIO_TRANS_SHIFT(trans))
This drops the spaces after #define... the idea is something like this:
#define REGISTER_OFFSET
#define REGISTER_CONTENTS
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
> #define _AUD_TCA_DP_2DOT0_CTRL 0x650bc
> #define _AUD_TCB_DP_2DOT0_CTRL 0x651bc
--
Jani Nikula, Intel
next prev parent reply other threads:[~2026-05-29 16:32 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-28 9:30 [PATCH v2 0/4] drm/i915/display: harden some bit-shifting operations Luca Coelho
2026-05-28 9:30 ` [PATCH v2 1/4] drm/i915/display: harden masks in HSW_AUD_PIN_ELD_CP_VLD macros Luca Coelho
2026-05-29 16:32 ` Jani Nikula [this message]
2026-05-28 9:30 ` [PATCH v2 2/4] drm/i915/display: harden shifts in ICL_DPCLKA_CFGCR0_DDI_CLK_SEL macros Luca Coelho
2026-05-28 9:30 ` [PATCH v2 3/4] drm/i915/display: harden shift in intel_ddi_compute_config_late() Luca Coelho
2026-05-28 9:30 ` [PATCH v2 4/4] drm/i915/display: remove unnecessary PHY_NONE definition Luca Coelho
2026-05-28 10:49 ` ✗ i915.CI.BAT: failure for drm/i915/display: harden some bit-shifting operations (rev2) Patchwork
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