Re: [Intel-gfx] [PATCH v3 4/4] drm/i915: Set copy engine arbitration for Wa_16018031267 / Wa_16018063123

[Nirmoy Das <nirmoy.das@linux.intel.com>]

On 10/23/2023 5:24 PM, Andrzej Hajda wrote:
> On 23.10.2023 11:55, Nirmoy Das wrote:
>> Hi Andrzej,
>>
>> On 10/23/2023 9:41 AM, Andrzej Hajda wrote:
>>> From: Jonathan Cavitt <jonathan.cavitt@intel.com>
>>>
>>> Set copy engine arbitration into round robin mode
>>> for part of Wa_16018031267 / Wa_16018063123 mitigation.
>>>
>>> Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
>>> Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
>>> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
>>> ---
>>>   drivers/gpu/drm/i915/gt/intel_engine_regs.h | 3 +++
>>>   drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++++
>>>   2 files changed, 8 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_regs.h 
>>> b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
>>> index b8618ee3e3041a..c0c8c12edea104 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_engine_regs.h
>>> +++ b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
>>> @@ -124,6 +124,9 @@
>>>   #define RING_INDIRECT_CTX(base)            _MMIO((base) + 0x1c4) 
>>> /* gen8+ */
>>>   #define RING_INDIRECT_CTX_OFFSET(base)        _MMIO((base) + 
>>> 0x1c8) /* gen8+ */
>>>   #define ECOSKPD(base)                _MMIO((base) + 0x1d0)
>>> +#define   XEHP_BLITTER_SCHEDULING_MODE_MASK REG_GENMASK(12, 11)
>>> +#define   XEHP_BLITTER_ROUND_ROBIN_MODE        \
>>> +        REG_FIELD_PREP(XEHP_BLITTER_SCHEDULING_MODE_MASK, 1)
>>>   #define   ECO_CONSTANT_BUFFER_SR_DISABLE    REG_BIT(4)
>>>   #define   ECO_GATING_CX_ONLY            REG_BIT(3)
>>>   #define   GEN6_BLITTER_FBC_NOTIFY        REG_BIT(3)
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
>>> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>> index 192ac0e59afa13..108d9326735910 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>> @@ -2782,6 +2782,11 @@ xcs_engine_wa_init(struct intel_engine_cs 
>>> *engine, struct i915_wa_list *wal)
>>>                RING_SEMA_WAIT_POLL(engine->mmio_base),
>>>                1);
>>>       }
>>> +    /* Wa_16018031267, Wa_16018063123 */
>>> +    if (NEEDS_FASTCOLOR_BLT_WABB(engine))
>>
>>
>> Not sure if I missed any previous discussion on this, the WA talked 
>> about applying this on main copy engine. This needs to be taken into 
>> account in
>>
>> NEEDS_FASTCOLOR_BLT_WABB()
>
> Do you mean we need to check if instance == 0? Now above macro checks 
> if it is copy engine.


Yes, The WA should be limited to  BCS0.

>
>
>>
>>> +        wa_masked_field_set(wal, ECOSKPD(engine->mmio_base),
>>> +                    XEHP_BLITTER_SCHEDULING_MODE_MASK,
>>> +                    XEHP_BLITTER_ROUND_ROBIN_MODE);
>>>   }
>>
>> This function sets masked_reg = true and will not read the register 
>> back and I remember MattR asked internally to not use that if that is 
>> not required.
>
> IIRC, wa_masked_field_set sets read_mask, so read back is performed, 
> anyway it is the only function (beside low level wa_add), which works 
> on fields(not bits). Are you sure?


Yes, you are right. I misread something. Please ignore that comment.


Regards,

Nirmoy

>
> Regards
> Andrzej
>
>>
>>
>> With those two concern handled this is  Reviewed-by: Nirmoy Das 
>> <nirmoy.das@intel.com>
>>
>>
>> Regards,
>>
>> Nirmoy
>>
>>>   static void
>>>
>