messages from 2012-03-16 23:18:07 to 2012-03-22 15:41:34 UTC [more...]
[PATCH] drm/i915: Sanitize BIOS debugging bits from PIPECONF
2012-03-22 15:40 UTC (2+ messages)
[PATCH 1/2] drm/i915: Reorganise rules for get_fence/put_fence
2012-03-22 15:10 UTC (2+ messages)
` [PATCH 2/2] drm/i915: Remove fence pipelining infrastructure
[RFC] ValleyView support
2012-03-22 15:03 UTC (61+ messages)
` [PATCH 01/25] drm/i915: move NEEDS_FORCE_WAKE to i915_drv.c
` [PATCH 02/25] drm/i915: add debug message when EDID fetch fails
` [PATCH 03/25] drm/i915: re-order GT IIR bit definitions
` [PATCH 04/25] drm/i915: Add basic support for parsing of VBT OEM Custom Block
` [PATCH 05/25] drm/i915: add DPIO read/write functions for ValleyView
` [PATCH 06/25] drm/i915: add ValleyView registers, stub code, and watermark support
` [PATCH 07/25] drm/i915: split out DPLL update code from i9xx_crtc_mode_set
` [PATCH 08/25] drm/i915: ValleyView mode setting limits and PLL functions
` [PATCH 09/25] drm/915: program driain latency regs on ValleyView
` [PATCH 10/25] drm/i915: Enable DP panel power sequencing for ValleyView
` [PATCH 11/25] drm/i915: Enable HDMI on ValleyView
` [PATCH 12/25] agp/intel: map more registers for use by the GTT code
` [PATCH 13/25] agp/intel: add Valleyview specific PTE entry function
` [PATCH 14/25] agp/intel: always use uncached mappings on VLV
` [PATCH 15/25] drm/i915: add ValleyView specific CRT detect function
` [PATCH 16/25] drm/i915: add ValleyView specific force wake get/put functions
` [PATCH 17/25] drm/i915: ValleyView cacheability is different
` [PATCH 18/25] drm/i915: ValleyView IRQ support
` [PATCH 19/25] drm/i915: display regs are at 0x180000 on ValleyView
` [PATCH 20/25] drm/i915: check for disabled interrupts "
` [PATCH 21/25] drm/i915: add HDMI and DP port enumeration "
` [PATCH 22/25] drm/i915: remove some unneeded debug messages
` [PATCH 23/25] drm/i915: add ValleyView clock gating init
` [PATCH 24/25] drm/i915: add has_turbo bit to driver info struct
` [PATCH 25/25] drm/i915: don't write ring regs until they're set up
[RFC] [PATCH 00/38] Haswell
2012-03-22 12:28 UTC (60+ messages)
` [PATCH 01/37] drm/i915: add Haswell devices and their PCI IDs
` [PATCH 02/37] drm/i915: add support for LynxPoint PCH
` [PATCH 03/37] drm/i915: add HAS_PLL_SPLIT macro
` [PATCH 04/37] drm/i915: add haswell into the PCH SPLIT company
` [PATCH 05/37] drm/i915: add support for power wells
` [PATCH 06/37] drm/i915: add DDI registers
` [PATCH 07/37] drm/i915: add DP_TP_CTL registers
` [PATCH 08/37] drm/i915: add DP_TP_STATUS registers
` [PATCH 09/37] drm/i915: add definitions for DDI_BUF_CTL registers
` [PATCH 10/37] drm/i915: add definition of LPT FDI port width registers
` [PATCH 11/37] drm/i915: add definition of DDI buffer translations regs
` [PATCH 12/37] drm/i915: add SBI registers
` [PATCH 13/37] drm/i915: add support for SBI ops
` [PATCH 14/37] drm/i915: add PIXCLK_GATE register
` [PATCH 15/37] drm/i915: add S PLL control
` [PATCH 16/37] drm/i915: add port clock selection support for HSW
` [PATCH 17/37] drm/i915: add SSC offsets for SBI access
` [PATCH 18/37] drm/i915: add GTC registers
` [PATCH 19/37] drm/i915: add LCPLL control registers
` [PATCH 20/37] drm/i915: add WM_LINETIME registers
` [PATCH 21/37] drm/i915: calculate watermarks on Gen7 archs in one place
` [PATCH 22/37] drm/i915: program WM_LINETIME on Haswell
` [PATCH 23/37] drm/i915: do not set 6BPP dithering on haswell
` [PATCH 24/37] drm/i915: share forcewaking code between IVB and HSW
` [PATCH 25/37] drm/i915: haswell has 3 pipes as well
` [PATCH 26/37] drm/i915: reuse Ivybridge interrupts code for Haswell
` [PATCH 27/37] drm/i915: share pipe count handling with Ivybridge
` [PATCH 28/37] drm/i915: share IVB cursor routine with Haswell
` [PATCH 29/37] drm/i915: enable power wells on haswell init
` [PATCH 30/37] drm/i915: disable rc6 on haswell for now
` [PATCH 31/37] drm/i915: enable PCH earlier
` [PATCH 32/37] drm/i915: perform Haswell DDI link training in FDI mode
` [PATCH 33/37] drm/i915: double-write DDI translation table
` [PATCH 34/37] drm/i915: do not use fdi_normal_train on haswell
` [PATCH 35/37] drm/i915: program iCLKIP on Lynx Point
` [PATCH 36/37] drm/i915: add warning when using old bits on Haswell/LPT
` [PATCH 37/37] drm/i915: dump registers read/write ops
[PATCH 0/2] semaphorify the pageflip BO (if possible)
2012-03-22 9:56 UTC (5+ messages)
` [PATCH 1/2] drm/i915: extract ring sync code
` [PATCH 2/2] drm/i915: use semaphores for the display plane
3d driver
2012-03-22 5:30 UTC
[PATCH] drm/i915: properly restore the ppgtt page directory on resume
2012-03-21 23:14 UTC
[PATCH 0/2 v6] drm/i915: LVDS channel mode fixes
2012-03-21 22:31 UTC (4+ messages)
` [PATCH 1/2] drm/i915: Check VBIOS value for determining LVDS dual channel mode, too
` [PATCH 2/2] drm/i915: Add lvds_channel module option
RFC: i915 arch changes to better support new chipsets
2012-03-21 20:41 UTC (6+ messages)
[PATCH] drm/i915: Mark untiled BLT commands as fenced on gen2/3
2012-03-21 10:48 UTC
pipe notify for ivb
2012-03-20 21:53 UTC
[PATCH 0/5] aliasing ppgtt, advanced things
2012-03-20 20:57 UTC (4+ messages)
` [PATCH 3/5] drm/i915: implement SNB workaround for lazy global gtt
[PATCH 0/2 v5] drm/i915: LVDS channel mode fixes
2012-03-20 18:35 UTC (8+ messages)
` [PATCH 1/2] drm/i915: Check VBIOS value for determining LVDS dual channel mode, too
` [PATCH 2/2] drm/i915: Add lvds_channel module option
[PATCH] drm/i915: treat src w & h as fixed point in sprite handling code
2012-03-20 17:59 UTC
[RFC] Try harder to allocate an mmap offset
2012-03-20 13:59 UTC (5+ messages)
` [PATCH 4/5] drm/i915: Remove the deferred-free list
[PATCH] drm/i915: IVB missed irqs w/a
2012-03-20 2:18 UTC (2+ messages)
[PATCH] intel: Add some PCI IDs for Haswell
2012-03-19 21:15 UTC
[PATCH 0/2 v4] drm/i915: LVDS channel mode fixes
2012-03-19 14:21 UTC (10+ messages)
` [PATCH 1/2] drm/i915: Check VBIOS value for determining LVDS dual channel mode, too
` [PATCH 2/2] drm/i915: Add lvds_channel module option
[PATCH 00/18] i915 HW Context Support
2012-03-19 10:14 UTC (21+ messages)
` [PATCH 01/18] drm/i915: CXT_SIZE register offsets added
` [PATCH 02/18] drm/i915: preliminary context support
` [PATCH 03/18] drm/i915: context basic create & destroy
` [PATCH 04/18] drm/i915: add context information to objects
` [PATCH 05/18] drm/i915: context switch implementation
` [PATCH 06/18] drm/i915: trace events for contexts
` [PATCH 07/18] drm/i915: Ivybridge MI_ARB_ON_OFF context w/a
` [PATCH 08/18] drm/i915: PIPE_CONTROL_TLB_INVALIDATE
` [PATCH 09/18] drm/i915: possibly invalidate TLB before context switch
` [PATCH 10/18] drm/i915: use the default context
` [PATCH 11/18] drm/i915: switch to default context on idle
` [PATCH 12/18] drm/i915: try to reset the gpu before unload
` [PATCH 13/18] drm/i915/context: create & destroy ioctls
` [PATCH 14/18] drm/i915/context: switch contexts with execbuf2
` [PATCH 15/18] drm/i915/context: add params
` [PATCH 16/18] drm/i915/context: anonymous context interfaces
` [PATCH 17/18] drm/i915: Ironlake rc6 can use "
` [PATCH 18/18] drm/i915: try to enable rc6 on Ironlake... again
how to enable "wait for vertical sync" on i915 framebuffer driver?
2012-03-19 8:22 UTC
VA-API brightness property
2012-03-19 1:51 UTC (3+ messages)
Updated -next
2012-03-18 21:20 UTC (3+ messages)
[PATCH 0/2] Two patches relating to ring initialization failure
2012-03-18 20:33 UTC (6+ messages)
` [PATCH 1/2] drm/i915: Add BUG_ON when ring->private is NULL
` [PATCH 2/2] drm/i915: Add wait_for in init_ring_common
Thinkpad T420 and single/dual channel lvds
2012-03-18 20:26 UTC (14+ messages)
[PATCH 1/2] drm/i915: Pull MTRR setup to its own function
2012-03-18 17:48 UTC (3+ messages)
` [PATCH 2/2] drm/i915: Don't do MTRR setup if PAT is enabled
Sandy bridge GPU does not support alpha channel?
2012-03-17 8:45 UTC
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