messages from 2019-10-25 14:48:03 to 2019-10-26 07:28:09 UTC [more...]
[PATCH] drm/i915/tgl: Adjust the location of RING_MI_MODE in the context image
2019-10-26 7:28 UTC (3+ messages)
` [Intel-gfx] "
` ✓ Fi.CI.BAT: success for drm/i915/tgl: Adjust the location of RING_MI_MODE in the context image (rev2)
[PATCH 0/5] DP AUX updates
2019-10-26 6:47 UTC (38+ messages)
` [Intel-gfx] "
` [PATCH 1/5] drm/i915/tgl: Handle AUX interrupts for TC ports
` [Intel-gfx] "
` [PATCH 2/5] drm/i915: Drop unused AUX register offsets
` [Intel-gfx] "
` [PATCH 3/5] drm/i915: Add missing AUX channel H & I support
` [Intel-gfx] "
` [PATCH 4/5] drm/i915: Provide more information on DP AUX failures
` [Intel-gfx] "
` [PATCH 5/5] drm/i915/tgl: Add AUX B & C to DC_OFF_POWER_DOMAINS
` [Intel-gfx] "
` ✗ Fi.CI.BUILD: failure for DP AUX updates
` [Intel-gfx] "
` ✗ Fi.CI.CHECKPATCH: warning for DP AUX updates (rev2)
` [Intel-gfx] "
` ✗ Fi.CI.BAT: failure "
` [Intel-gfx] "
` ✗ Fi.CI.CHECKPATCH: warning for DP AUX updates (rev3)
` [Intel-gfx] "
` ✓ Fi.CI.BAT: success "
` [Intel-gfx] "
[PATCH] drm/i914/guc: Fix resume on platforms w/o GuC submission but enabled
2019-10-26 5:53 UTC (3+ messages)
` ✗ Fi.CI.IGT: failure for "
` [Intel-gfx] "
[PATCH] drm/i915/selftests: Mock the engine sorting for easy validation
2019-10-26 4:52 UTC (3+ messages)
` ✓ Fi.CI.IGT: success for "
` [Intel-gfx] "
[PATCH 1/2] drm/i915: Encapsulate kconfig constant values inside boolean predicates
2019-10-26 4:06 UTC (7+ messages)
` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] "
` [Intel-gfx] "
` ✗ Fi.CI.BAT: failure "
` [Intel-gfx] "
` [Intel-gfx] [PATCH 1/2] "
[PATCH 1/3] drm/i915: Use _PICK() for CHICKEN_TRANS()
2019-10-26 2:55 UTC (3+ messages)
` ✗ Fi.CI.IGT: failure for series starting with [1/3] "
` [Intel-gfx] "
[PATCH 1/2] drm/i915/uc: define GuC and HuC binaries for TGL
2019-10-26 2:35 UTC (8+ messages)
` [Intel-gfx] "
` [PATCH 2/2] HAX: force enable_guc=2
` [Intel-gfx] "
` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/uc: define GuC and HuC binaries for TGL
` [Intel-gfx] "
` ✓ Fi.CI.BAT: success "
` [Intel-gfx] "
[PATCH 1/5] drm/i915: Add two spaces before the SKL_DFSM registers
2019-10-26 2:04 UTC (12+ messages)
` [Intel-gfx] "
` [PATCH 2/5] drm/i915/display: Handle fused off HDCP
` [Intel-gfx] "
` [PATCH 3/5] drm/i915/display: Check if FBC is fused off
` [Intel-gfx] "
` [PATCH 4/5] drm/i915/display/icl+: Check if DMC "
` [Intel-gfx] "
` [PATCH 5/5] drm/i915/display/cnl+: Handle fused off DSC
` [Intel-gfx] "
` ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915: Add two spaces before the SKL_DFSM registers
` [Intel-gfx] "
CI testing of persistence
2019-10-26 1:58 UTC (3+ messages)
` ✓ Fi.CI.IGT: success for drm/i915/gem: Make context persistence optional
` [Intel-gfx] "
[PATCH] drm/i915/tgl: Adjust the location of RING_MI_MODE in the context image
2019-10-26 1:40 UTC (4+ messages)
` [Intel-gfx] "
` ✗ Fi.CI.BAT: failure for "
` [Intel-gfx] "
[PATCH] drm/i915/gem: Limit the blitter sizes to ensure low preemption latency
2019-10-26 1:24 UTC (4+ messages)
` [Intel-gfx] "
` ✗ Fi.CI.BAT: failure for "
` [Intel-gfx] "
[CI] PR for TGL GuC/HuC binaries
2019-10-26 0:09 UTC (2+ messages)
` [Intel-gfx] "
[PATCH v2 1/2] drm/i915/perf: Add helper macros for comparing with whitelisted registers
2019-10-26 0:09 UTC (10+ messages)
` [Intel-gfx] "
` [PATCH v2 2/2] drm/i915/tgl: Add perf support on TGL
` [Intel-gfx] "
` ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/2] drm/i915/perf: Add helper macros for comparing with whitelisted registers
` [Intel-gfx] "
` ✗ Fi.CI.SPARSE: "
` [Intel-gfx] "
` ✗ Fi.CI.BAT: failure "
` [Intel-gfx] "
[PATCH v2] drm/i915/selftests/blt: add some kthreads into the mix
2019-10-25 23:42 UTC (4+ messages)
` [Intel-gfx] "
` ✗ Fi.CI.BAT: failure for drm/i915/selftests/blt: add some kthreads into the mix (rev2)
` [Intel-gfx] "
[PATCH 1/2] drm/i915: Remove nonpriv flags when srm/lrm
2019-10-25 23:17 UTC (3+ messages)
` ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915: Remove nonpriv flags when srm/lrm (rev2)
` [Intel-gfx] "
[PATCH] drm/i915/tc: Clear DKL_TX_PMD_LANE_SUS before program voltage swing
2019-10-25 23:03 UTC (6+ messages)
` ✓ Fi.CI.IGT: success for "
` [Intel-gfx] "
` [Intel-gfx] [PATCH] "
[PATCH] drm/i915: Allow gen11 to use over 32k long strides
2019-10-25 22:08 UTC (3+ messages)
` ✗ Fi.CI.IGT: failure for drm/i915: Allow gen11 to use over 32k long strides (rev2)
` [Intel-gfx] "
[PATCH i-g-t] i915/pm_rps: Wait for the actual frequency to settle
2019-10-25 21:49 UTC (2+ messages)
` [Intel-gfx] "
[PATCH] drm/i915/pmu: Initialise the spinlock before registering
2019-10-25 21:33 UTC (6+ messages)
` [Intel-gfx] "
` ✓ Fi.CI.BAT: success for "
` [Intel-gfx] "
CI testing of persistence and sysfs
2019-10-25 21:29 UTC (6+ messages)
` [PATCH 01/11] drm/i915/gem: Make context persistence optional
` [Intel-gfx] "
[CI 1/7] drm/i915: support creating LMEM objects
2019-10-25 20:32 UTC (20+ messages)
` [Intel-gfx] "
` [CI 2/7] drm/i915: setup io-mapping for LMEM
` [Intel-gfx] "
` [CI 3/7] drm/i915/lmem: support kernel mapping
` [Intel-gfx] "
` [CI 4/7] drm/i915/selftests: add write-dword test for LMEM
` [Intel-gfx] "
` [CI 5/7] drm/i915/selftests: extend coverage to include LMEM huge-pages
` [Intel-gfx] "
` [CI 6/7] drm/i915/selftests: prefer random sizes for the huge-GTT-page smoke tests
` [Intel-gfx] "
` [CI 7/7] drm/i915/selftests: add sanity selftest for huge-GTT-pages
` [Intel-gfx] "
` ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/7] drm/i915: support creating LMEM objects
` [Intel-gfx] "
` ✗ Fi.CI.SPARSE: "
` [Intel-gfx] "
` ✓ Fi.CI.BAT: success "
` [Intel-gfx] "
[RFC 0/5] Per client engine busyness (all aboard the sysfs train!)
2019-10-25 20:12 UTC (8+ messages)
` [RFC 5/5] drm/i915: Add sysfs toggle to enable per-client engine stats
` [Intel-gfx] "
` ✗ Fi.CI.CHECKPATCH: warning for Per client engine busyness (all aboard the sysfs train!)
` [Intel-gfx] "
` ✗ Fi.CI.BAT: failure "
` [Intel-gfx] "
[PATCH] drm/dp: Add function to parse EDID descriptors for adaptive sync limits
2019-10-25 20:02 UTC (4+ messages)
` [Intel-gfx] "
[PATCH] drm/i915: Program LUT before intel_color_commit() if LUT was not previously set
2019-10-25 19:45 UTC (6+ messages)
` [Intel-gfx] "
[PATCH 2/2] drm/i915/cml: Separate U sereis pci id from origianl list
2019-10-25 20:25 UTC (4+ messages)
` [PATCH v2 "
` [Intel-gfx] "
[PATCH 1/4] drm/edid: Make drm_get_cea_aspect_ratio() static
2019-10-25 19:19 UTC (7+ messages)
` [PATCH 4/4] drm/edid: Prep for HDMI VIC aspect ratio (WIP)
` [Intel-gfx] "
[PATCH i-g-t] i915/gem_exec_suspend: Exercise S0 (aka s2idle)
2019-10-25 19:16 UTC (3+ messages)
` [igt-dev] "
` [Intel-gfx] "
[PATCH] drm: Add support for integrated privacy screens
2019-10-25 19:03 UTC (7+ messages)
` [Intel-gfx] "
[PATCH v8 0/2] Refactor Gen11+ SAGV support
2019-10-25 19:01 UTC (4+ messages)
` [PATCH v8 2/2] drm/i915: Restrict qgv points which don't have enough bandwidth
` [Intel-gfx] "
[PATCH] CI: Test revert some of the documentation fixes
2019-10-25 18:41 UTC (7+ messages)
` ✗ Fi.CI.CHECKPATCH: warning for "
` [Intel-gfx] "
` ✗ Fi.CI.DOCS: "
` [Intel-gfx] "
` ✗ Fi.CI.BAT: failure "
` [Intel-gfx] "
[PATCH v2 0/5] Update VSC SDP / HDR Metadata SDP states on pipe updates
2019-10-25 17:43 UTC (3+ messages)
` ✓ Fi.CI.BAT: success for Update VSC SDP / HDR Metadata SDP states on pipe updates. (rev2)
` [Intel-gfx] "
[PATCH] drm/i915: capture aux page table error register
2019-10-25 17:31 UTC (9+ messages)
` [Intel-gfx] "
` ✗ Fi.CI.CHECKPATCH: warning for "
` [Intel-gfx] "
` ✗ Fi.CI.BAT: failure "
` [Intel-gfx] "
[PATCH] drm/i915: Fix PCH reference clock for FDI on HSW/BDW
2019-10-25 17:24 UTC (4+ messages)
` [Intel-gfx] "
[PATCH 1/2] drm/i915/cml: Remove unsupport PCI ID
2019-10-25 17:17 UTC (3+ messages)
` ✗ Fi.CI.BUILD: failure for series starting with [v4] drm/i915/cml: Remove unsupport PCI ID (rev5)
` [Intel-gfx] "
[PATCH v2] kernel-doc: rename the kernel-doc directive 'functions' to 'identifiers'
2019-10-25 14:48 UTC (5+ messages)
` [Intel-gfx] "
[PATCH v2 1/2] commit 'a7b4deeb02b9 ("drm/i915/cml: Add CML PCI IDS)' introduced new PCI ID that CML support. But some sku is not support yet so remove them
2019-10-25 20:32 UTC (4+ messages)
` [PATCH v4] drm/i915/cml: Remove unsupport PCI ID
` [Intel-gfx] "
[PATCH 1/4] drm/i915: Add is_dgfx to device info
2019-10-25 16:49 UTC (4+ messages)
` [PATCH 3/4] drm/i915: do not set MOCS control values on dgfx
` [Intel-gfx] "
[PATCH] drm/i915/selftests/blt: add some kthreads into the mix
2019-10-25 16:36 UTC (5+ messages)
` ✗ Fi.CI.CHECKPATCH: warning for "
` [Intel-gfx] "
` ✗ Fi.CI.BAT: failure "
` [Intel-gfx] "
[PATCH i-g-t] lib/i915: Use explicit iterator names in for_each_engine()
2019-10-25 16:28 UTC (5+ messages)
` [Intel-gfx] "
[RFC i-g-t 0/1] Per client engine busyness
2019-10-25 15:38 UTC (6+ messages)
` [RFC i-g-t 1/1] intel-gpu-top: Support for client stats
` [igt-dev] "
` [Intel-gfx] "
[PATCH] drm/i915/dsb: Remove PIN_MAPPABLE from the DSB object VMA
2019-10-25 15:22 UTC (3+ messages)
` [Intel-gfx] "
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