messages from 2019-10-25 19:21:53 to 2019-10-27 11:26:10 UTC [more...]
[CI 1/7] drm/i915: support creating LMEM objects
2019-10-27 11:26 UTC (8+ messages)
` ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/7] "
` [Intel-gfx] "
` ✗ Fi.CI.SPARSE: "
` [Intel-gfx] "
` ✓ Fi.CI.BAT: success "
` [Intel-gfx] "
` ✓ Fi.CI.IGT: "
[PATCH] drm/i915/execlists: Simply walk back along request timeline on reset
2019-10-27 11:13 UTC (2+ messages)
` [Intel-gfx] "
[PATCH] drm/i915/execlists: Simply walk back along request timeline on reset
2019-10-27 10:42 UTC (4+ messages)
` [Intel-gfx] "
` ✗ Fi.CI.BAT: failure for drm/i915/execlists: Simply walk back along request timeline on reset (rev4)
` [Intel-gfx] "
[PATCH v2 0/5] Update VSC SDP / HDR Metadata SDP states on pipe updates
2019-10-27 7:47 UTC (3+ messages)
` ✓ Fi.CI.IGT: success for Update VSC SDP / HDR Metadata SDP states on pipe updates. (rev2)
` [Intel-gfx] "
[CI 1/7] drm/i915: support creating LMEM objects
2019-10-27 4:45 UTC (3+ messages)
` ✓ Fi.CI.IGT: success for series starting with [CI,1/7] drm/i915: support creating LMEM objects (rev2)
` [Intel-gfx] "
[CI] drm/i915: Split memory_region initialisation into its own file
2019-10-26 21:15 UTC (4+ messages)
` [Intel-gfx] "
` ✓ Fi.CI.BAT: success for drm/i915: Split memory_region initialisation into its own file (rev2)
` [Intel-gfx] "
[PATCH] drm/i915/selftests: Tweak the default subtest runtime
2019-10-26 21:13 UTC (3+ messages)
` ✓ Fi.CI.IGT: success for "
` [Intel-gfx] "
[PATCH] drm/i915/rps: Flip interpretation of ips fmin/fmax to max rps
2019-10-26 20:43 UTC (4+ messages)
` [Intel-gfx] "
` ✓ Fi.CI.BAT: success for "
` [Intel-gfx] "
[PATCH] drm/i915/execlists: Simply walk back along request timeline on reset
2019-10-26 20:37 UTC (8+ messages)
` [Intel-gfx] "
` ✓ Fi.CI.BAT: success for drm/i915/execlists: Simply walk back along request timeline on reset (rev3)
` [Intel-gfx] "
[PATCH i-g-t 1/2] lib: Restore i915.reset before testing it in igt_allow_hang()
2019-10-26 19:34 UTC (4+ messages)
` [Intel-gfx] "
` [PATCH i-g-t 2/2] i915/gem_ctx_exec: Enable resets for basic-nohangcheck
` [Intel-gfx] "
[PATCH] drm/i915: Move intel_engine_context_in/out into intel_lrc.c
2019-10-26 19:07 UTC (3+ messages)
` ✗ Fi.CI.IGT: failure for "
` [Intel-gfx] "
[PATCH i-g-t] lib/i915: Use explicit iterator names in for_each_engine()
2019-10-26 17:55 UTC (5+ messages)
` [Intel-gfx] "
[PATCH i-g-t] i915/pm_rps: Wait for the actual frequency to settle
2019-10-26 17:40 UTC (4+ messages)
` [Intel-gfx] "
[PATCH] drm: Add support for integrated privacy screens
2019-10-26 17:18 UTC (8+ messages)
` [Intel-gfx] "
[PATCH] drm/i915/tgl: Adjust the location of RING_MI_MODE in the context image
2019-10-26 14:46 UTC (6+ messages)
` [Intel-gfx] "
` ✓ Fi.CI.BAT: success for drm/i915/tgl: Adjust the location of RING_MI_MODE in the context image (rev2)
` [Intel-gfx] "
[CI 1/2] drm/i915: Extract GT render power state management
2019-10-26 14:07 UTC (3+ messages)
` ✗ Fi.CI.IGT: failure for series starting with [CI,1/2] "
` [Intel-gfx] "
[PATCH] drm/i915/execlists: Skip over foreign requests on the context timeline
2019-10-26 11:24 UTC (4+ messages)
` [Intel-gfx] "
` ✓ Fi.CI.BAT: success for "
` [Intel-gfx] "
[PATCH 1/2] drm/i915/uc: define GuC and HuC binaries for TGL
2019-10-26 10:44 UTC (10+ messages)
` [Intel-gfx] "
` [PATCH 2/2] HAX: force enable_guc=2
` [Intel-gfx] "
` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/uc: define GuC and HuC binaries for TGL
` [Intel-gfx] "
` ✓ Fi.CI.BAT: success "
` [Intel-gfx] "
[PATCH] drm/i915/execlists: Verify context register state before execution
2019-10-26 10:39 UTC (4+ messages)
` [Intel-gfx] "
` ✗ Fi.CI.BAT: failure for "
` [Intel-gfx] "
[CI] drm/i915/gem: Make context persistence optional
2019-10-26 10:21 UTC (4+ messages)
` [Intel-gfx] "
` ✗ Fi.CI.BAT: failure for drm/i915/gem: Make context persistence optional (rev2)
` [Intel-gfx] "
[PATCH 1/4] drm/i915: Add is_dgfx to device info
2019-10-26 9:03 UTC (3+ messages)
` ✓ Fi.CI.IGT: success for series starting with [1/4] "
` [Intel-gfx] "
[PATCH 0/5] DP AUX updates
2019-10-26 8:57 UTC (40+ messages)
` [Intel-gfx] "
` [PATCH 1/5] drm/i915/tgl: Handle AUX interrupts for TC ports
` [Intel-gfx] "
` [PATCH 2/5] drm/i915: Drop unused AUX register offsets
` [Intel-gfx] "
` [PATCH 3/5] drm/i915: Add missing AUX channel H & I support
` [Intel-gfx] "
` [PATCH 4/5] drm/i915: Provide more information on DP AUX failures
` [Intel-gfx] "
` [PATCH 5/5] drm/i915/tgl: Add AUX B & C to DC_OFF_POWER_DOMAINS
` [Intel-gfx] "
` ✗ Fi.CI.BUILD: failure for DP AUX updates
` [Intel-gfx] "
` ✗ Fi.CI.CHECKPATCH: warning for DP AUX updates (rev2)
` [Intel-gfx] "
` ✗ Fi.CI.BAT: failure "
` [Intel-gfx] "
` ✗ Fi.CI.CHECKPATCH: warning for DP AUX updates (rev3)
` [Intel-gfx] "
` ✓ Fi.CI.BAT: success "
` [Intel-gfx] "
[PATCH] drm/i915/tgl: Adjust the location of RING_MI_MODE in the context image
2019-10-26 8:46 UTC (4+ messages)
` [Intel-gfx] "
` ✓ Fi.CI.BAT: success for drm/i915/tgl: Adjust the location of RING_MI_MODE in the context image (rev3)
` [Intel-gfx] "
[PATCH] drm/i915/tgl: Handle AUX interrupts for TC ports
2019-10-26 8:01 UTC (3+ messages)
` ✗ Fi.CI.IGT: failure for drm/i915/tgl: Handle AUX interrupts for TC ports (rev2)
` [Intel-gfx] "
[PATCH] drm/i914/guc: Fix resume on platforms w/o GuC submission but enabled
2019-10-26 5:53 UTC (3+ messages)
` ✗ Fi.CI.IGT: failure for "
` [Intel-gfx] "
[PATCH] drm/i915/selftests: Mock the engine sorting for easy validation
2019-10-26 4:52 UTC (3+ messages)
` ✓ Fi.CI.IGT: success for "
` [Intel-gfx] "
[PATCH 1/2] drm/i915: Encapsulate kconfig constant values inside boolean predicates
2019-10-26 4:06 UTC (5+ messages)
` ✗ Fi.CI.BAT: failure for series starting with [1/2] "
` [Intel-gfx] "
` [Intel-gfx] [PATCH 1/2] "
[PATCH 1/3] drm/i915: Use _PICK() for CHICKEN_TRANS()
2019-10-26 2:55 UTC (3+ messages)
` ✗ Fi.CI.IGT: failure for series starting with [1/3] "
` [Intel-gfx] "
[PATCH 1/5] drm/i915: Add two spaces before the SKL_DFSM registers
2019-10-26 2:04 UTC (12+ messages)
` [Intel-gfx] "
` [PATCH 2/5] drm/i915/display: Handle fused off HDCP
` [Intel-gfx] "
` [PATCH 3/5] drm/i915/display: Check if FBC is fused off
` [Intel-gfx] "
` [PATCH 4/5] drm/i915/display/icl+: Check if DMC "
` [Intel-gfx] "
` [PATCH 5/5] drm/i915/display/cnl+: Handle fused off DSC
` [Intel-gfx] "
` ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915: Add two spaces before the SKL_DFSM registers
` [Intel-gfx] "
CI testing of persistence
2019-10-26 1:58 UTC (3+ messages)
` ✓ Fi.CI.IGT: success for drm/i915/gem: Make context persistence optional
` [Intel-gfx] "
[PATCH] drm/i915/tgl: Adjust the location of RING_MI_MODE in the context image
2019-10-26 1:40 UTC (4+ messages)
` [Intel-gfx] "
` ✗ Fi.CI.BAT: failure for "
` [Intel-gfx] "
[PATCH] drm/i915/gem: Limit the blitter sizes to ensure low preemption latency
2019-10-26 1:24 UTC (4+ messages)
` [Intel-gfx] "
` ✗ Fi.CI.BAT: failure for "
` [Intel-gfx] "
[CI] PR for TGL GuC/HuC binaries
2019-10-26 0:09 UTC (2+ messages)
` [Intel-gfx] "
[PATCH v2 1/2] drm/i915/perf: Add helper macros for comparing with whitelisted registers
2019-10-26 0:09 UTC (10+ messages)
` [Intel-gfx] "
` [PATCH v2 2/2] drm/i915/tgl: Add perf support on TGL
` [Intel-gfx] "
` ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/2] drm/i915/perf: Add helper macros for comparing with whitelisted registers
` [Intel-gfx] "
` ✗ Fi.CI.SPARSE: "
` [Intel-gfx] "
` ✗ Fi.CI.BAT: failure "
` [Intel-gfx] "
[PATCH v2] drm/i915/selftests/blt: add some kthreads into the mix
2019-10-25 23:42 UTC (3+ messages)
` ✗ Fi.CI.BAT: failure for drm/i915/selftests/blt: add some kthreads into the mix (rev2)
` [Intel-gfx] "
[PATCH 1/2] drm/i915: Remove nonpriv flags when srm/lrm
2019-10-25 23:17 UTC (3+ messages)
` ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915: Remove nonpriv flags when srm/lrm (rev2)
` [Intel-gfx] "
[PATCH] drm/i915/tc: Clear DKL_TX_PMD_LANE_SUS before program voltage swing
2019-10-25 23:03 UTC (6+ messages)
` ✓ Fi.CI.IGT: success for "
` [Intel-gfx] "
` [Intel-gfx] [PATCH] "
[PATCH] drm/i915: Allow gen11 to use over 32k long strides
2019-10-25 22:08 UTC (3+ messages)
` ✗ Fi.CI.IGT: failure for drm/i915: Allow gen11 to use over 32k long strides (rev2)
` [Intel-gfx] "
[PATCH] drm/i915/pmu: Initialise the spinlock before registering
2019-10-25 21:33 UTC (3+ messages)
` ✓ Fi.CI.BAT: success for "
` [Intel-gfx] "
CI testing of persistence and sysfs
2019-10-25 21:29 UTC (5+ messages)
` [PATCH 01/11] drm/i915/gem: Make context persistence optional
` [Intel-gfx] "
[RFC 0/5] Per client engine busyness (all aboard the sysfs train!)
2019-10-25 20:12 UTC (5+ messages)
` ✗ Fi.CI.CHECKPATCH: warning for "
` [Intel-gfx] "
` ✗ Fi.CI.BAT: failure "
` [Intel-gfx] "
[PATCH] drm/dp: Add function to parse EDID descriptors for adaptive sync limits
2019-10-25 20:02 UTC (4+ messages)
` [Intel-gfx] "
[PATCH] drm/i915: Program LUT before intel_color_commit() if LUT was not previously set
2019-10-25 19:45 UTC (6+ messages)
` [Intel-gfx] "
[PATCH 2/2] drm/i915/cml: Separate U sereis pci id from origianl list
2019-10-25 20:25 UTC (4+ messages)
` [PATCH v2 "
` [Intel-gfx] "
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