messages from 2020-07-09 08:49:51 to 2020-07-10 12:30:14 UTC [more...]
[Intel-gfx] [PATCH] drm/i915/gt: Be defensive in the face of false CS events
2020-07-10 12:30 UTC (4+ messages)
[Intel-gfx] s/obj->mm.lock//
2020-07-10 12:24 UTC (26+ messages)
` [Intel-gfx] [PATCH 03/20] drm/i915/gem: Don't drop the timeline lock during execbuf
` [Intel-gfx] [PATCH 04/20] drm/i915/gem: Rename execbuf.bind_link to unbound_link
` [Intel-gfx] [PATCH 05/20] drm/i915/gem: Break apart the early i915_vma_pin from execbuf object lookup
` [Intel-gfx] [PATCH 09/20] drm/i915/gem: Assign context id for async work
` [Intel-gfx] [PATCH 10/20] drm/i915: Export a preallocate variant of i915_active_acquire()
` [Intel-gfx] [PATCH 16/20] drm/i915/gem: Reintroduce multiple passes for reloc processing
` [Intel-gfx] [PATCH 19/20] drm/i915/gem: Replace i915_gem_object.mm.mutex with reservation_ww_class
[Intel-gfx] [PATCH] drm/i915: WARN if max vswing/pre-emphasis violates the DP spec
2020-07-10 12:02 UTC (5+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [RFC 00/60] DG1 LMEM enabling
2020-07-10 11:57 UTC (61+ messages)
` [Intel-gfx] [RFC 01/60] drm/i915: Add has_master_unit_irq flag
` [Intel-gfx] [RFC 02/60] drm/i915/dg1: add initial DG-1 definitions
` [Intel-gfx] [RFC 03/60] drm/i915/dg1: Add DG1 PCI IDs
` [Intel-gfx] [RFC 04/60] drm/i915/dg1: add support for the master unit interrupt
` [Intel-gfx] [RFC 05/60] drm/i915/dg1: Remove SHPD_FILTER_CNT register programming
` [Intel-gfx] [RFC 06/60] drm/i915/dg1: Add fake PCH
` [Intel-gfx] [RFC 07/60] drm/i915/dg1: Initialize RAWCLK properly
` [Intel-gfx] [RFC 08/60] drm/i915/dg1: Define MOCS table for DG1
` [Intel-gfx] [RFC 09/60] drm/i915/dg1: Add DG1 power wells
` [Intel-gfx] [RFC 10/60] drm/i915/dg1: Increase mmio size to 4MB
` [Intel-gfx] [RFC 11/60] drm/i915/dg1: Wait for pcode/uncore handshake at startup
` [Intel-gfx] [RFC 12/60] drm/i915/dg1: Add DPLL macros for DG1
` [Intel-gfx] [RFC 13/60] drm/i915/dg1: Add and setup DPLLs "
` [Intel-gfx] [RFC 14/60] drm/i915/dg1: Enable DPLL "
` [Intel-gfx] [RFC 15/60] drm/i915/dg1: add hpd interrupt handling
` [Intel-gfx] [RFC 16/60] drm/i915/dg1: invert HPD pins
` [Intel-gfx] [RFC 17/60] drm/i915/dg1: gmbus pin mapping
` [Intel-gfx] [RFC 18/60] drm/i915/dg1: Enable first 2 ports for DG1
` [Intel-gfx] [RFC 19/60] drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D
` [Intel-gfx] [RFC 20/60] drm/i915/dg1: Update comp master/slave relationships for PHYs
` [Intel-gfx] [RFC 21/60] drm/i915/dg1: Update voltage swing tables for DP
` [Intel-gfx] [RFC 22/60] drm/i915/dg1: provide port/phy mapping for vbt
` [Intel-gfx] [RFC 23/60] drm/i915/dg1: map/unmap pll clocks
` [Intel-gfx] [RFC 24/60] drm/i915/dg1: enable PORT C/D aka D/E
` [Intel-gfx] [RFC 25/60] drm/i915/dg1: Load DMC
` [Intel-gfx] [RFC 26/60] drm/i915/rkl: Add initial workarounds
` [Intel-gfx] [RFC 27/60] drm/i915/dg1: Add initial DG1 workarounds
` [Intel-gfx] [RFC 28/60] drm/i915/dg1: DG1 does not support DC6
` [Intel-gfx] [RFC 29/60] drm/i915/lmem: Limit block size to 4G
` [Intel-gfx] [RFC 30/60] drm/i915/lmem: Do not check r->sgt.pfn for NULL
` [Intel-gfx] [RFC 31/60] drm/i915/dgfx: define llc and snooping behaviour
` [Intel-gfx] [RFC 32/60] drm/i915/lmem: support pread
` [Intel-gfx] [RFC 33/60] drm/i915/lmem: support pwrite
` [Intel-gfx] [RFC 34/60] drm/i915: introduce kernel blitter_context
` [Intel-gfx] [RFC 35/60] drm/i915/query: Expose memory regions through the query uAPI
` [Intel-gfx] [RFC 36/60] drm/i915/uapi: introduce drm_i915_gem_create_ext
` [Intel-gfx] [RFC 37/60] drm/i915/lmem: allocate cmd ring in lmem
` [Intel-gfx] [RFC 38/60] drm/i915/dg1: Introduce dmabuf mmap to LMEM
` [Intel-gfx] [RFC 39/60] drm/i915: setup the LMEM region
` [Intel-gfx] [RFC 40/60] drm/i915: drop fake LMEM
` [Intel-gfx] [RFC 41/60] drm/i915: Distinction of memory regions
` [Intel-gfx] [RFC 42/60] drm/i915: PPGTT support
` [Intel-gfx] [RFC 43/60] drm/i915: support GGTT LMEM entries
` [Intel-gfx] [RFC 44/60] drm/i915: allocate context from LMEM
` [Intel-gfx] [RFC 45/60] drm/i915: move engine scratch to LMEM
` [Intel-gfx] [RFC 46/60] drm/i915: Provide a way to disable PCIe relaxed write ordering
` [Intel-gfx] [RFC 47/60] drm/i915: setup GPU device lmem region
` [Intel-gfx] [RFC 48/60] drm/i915: Fix object page offset within a region
` [Intel-gfx] [RFC 49/60] drm/i915: add i915_gem_object_is_devmem() function
` [Intel-gfx] [RFC 50/60] drm/i915: finish memory region support for stolen objects
` [Intel-gfx] [RFC 51/60] drm/i915/lmem: support optional CPU clearing for special internal use
` [Intel-gfx] [RFC 52/60] drm/i915/guc: put all guc objects in lmem when available
` [Intel-gfx] [RFC 53/60] drm/i915: Create stolen memory region from local memory
` [Intel-gfx] [RFC 54/60] drm/i915/lmem: Bypass aperture when lmem is available
` [Intel-gfx] [RFC 55/60] drm/i915/lmem: reset the lmem buffer created by fbdev
` [Intel-gfx] [RFC 56/60] drm/i915/dsb: Enable lmem for dsb
` [Intel-gfx] [RFC 57/60] drm/i915: Reintroduce mem->reserved
` [Intel-gfx] [RFC 58/60] drm/i915/dg1: Reserve first 1MB of local memory
` [Intel-gfx] [RFC 59/60] drm/i915: defer pd lmem block put to worker
` [Intel-gfx] [RFC 60/60] drm/i915/lmem: allocate HWSP in lmem
[Intel-gfx] [PATCH v4 1/5] drm/i915/display: Replace drm_i915_private in voltage swing functions by intel_encoder
2020-07-10 11:56 UTC (12+ messages)
` [Intel-gfx] [PATCH v4 2/5] drm/i915/display: Remove port and phy from voltage swing functions
` [Intel-gfx] [PATCH v4 4/5] drm/i915/display: Implement HOBL
` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v4,1/5] drm/i915/display: Replace drm_i915_private in voltage swing functions by intel_encoder (rev2)
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH] drm/fb-helper: Fix vt restore
2020-07-10 11:31 UTC (2+ messages)
[Intel-gfx] [PATCH 15/25] drm/tilcdc: Use standard drm_atomic_helper_commit
2020-07-10 11:16 UTC (3+ messages)
` [Intel-gfx] [PATCH] "
[Intel-gfx] [PATCH] drm/i915/perf: Use GTT when saving/restoring engine GPR
2020-07-10 9:43 UTC (10+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH i-g-t 1/6] lib/i915: Report unknown device as the future
2020-07-10 9:32 UTC (6+ messages)
` [Intel-gfx] [PATCH i-g-t 2/6] tools: Use the gt number stored in the device info
` [Intel-gfx] [PATCH i-g-t 3/6] lib/i915: Pick a subtest conformant name for an unknown engine
` [Intel-gfx] [PATCH i-g-t 4/6] i915/gem_close: Adapt to allow duplicate handles
` [Intel-gfx] [PATCH i-g-t 5/6] i915/gem_exec_schedule: Try to spot unfairness
` [Intel-gfx] [PATCH i-g-t 6/6] i915/gem_softpin: Active rebinds
[Intel-gfx] [PATCH] drm/i915/selftest: Check that GPR are restored across noa_wait
2020-07-10 5:34 UTC (3+ messages)
` [Intel-gfx] ✗ Fi.CI.BAT: failure for "
[Intel-gfx] [CI 1/2] drm/i915/perf: Use GTT when saving/restoring engine GPR
2020-07-10 2:47 UTC (4+ messages)
` [Intel-gfx] [CI 2/2] drm/i915/selftest: Check that GPR are restored across noa_wait
` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/2] drm/i915/perf: Use GTT when saving/restoring engine GPR
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [CI 1/6] drm/i915: Add has_master_unit_irq flag
2020-07-10 2:40 UTC (9+ messages)
` [Intel-gfx] [CI 2/6] drm/i915/dg1: add initial DG-1 definitions
` [Intel-gfx] [CI 3/6] drm/i915/dg1: Add DG1 PCI IDs
` [Intel-gfx] [CI 4/6] drm/i915/dg1: add support for the master unit interrupt
` [Intel-gfx] [CI 5/6] drm/i915/dg1: Remove SHPD_FILTER_CNT register programming
` [Intel-gfx] [CI 6/6] drm/i915/dg1: Add fake PCH
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/6] drm/i915: Add has_master_unit_irq flag
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [CI] drm/i915/gt: Optimise aliasing-ppgtt allocations
2020-07-09 22:26 UTC (3+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [PATCH v3 03/28] drm/i915/dg1: Add DG1 PCI IDs
2020-07-09 20:56 UTC (4+ messages)
[Intel-gfx] [PATCH] drm/i915/selftests: Fix compare functions provided for sorting
2020-07-09 19:52 UTC (4+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH 1/3] drm/edid: Allow looking for ext blocks starting from a specified index
2020-07-09 18:45 UTC (6+ messages)
` [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/edid: Allow looking for ext blocks starting from a specified index (rev2)
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH] drm/i915/tgl: Implement WAs 18011464164 and 22010931296
2020-07-09 17:18 UTC (4+ messages)
` [Intel-gfx] ✗ Fi.CI.IGT: failure for "
[Intel-gfx] [PATCH 00/25] dma-fence annotations, round 3
2020-07-09 15:38 UTC (16+ messages)
` [Intel-gfx] [PATCH 03/25] dma-buf.rst: Document why idenfinite fences are a bad idea
` [Intel-gfx] [PATCH 1/2] dma-buf.rst: Document why indefinite "
` [Intel-gfx] [PATCH 2/2] drm/virtio: Remove open-coded commit-tail function
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for dma-fence annotations, round 3 (rev6)
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH v4 00/15] acpi/pwm/i915: Convert pwm-crc and i915 driver's PWM code to use the atomic PWM API
2020-07-09 15:47 UTC (16+ messages)
` [Intel-gfx] [PATCH v4 04/16] pwm: lpss: Add range limit check for the base_unit register value
` [Intel-gfx] [PATCH v4 05/16] pwm: lpss: Use pwm_lpss_apply() when restoring state on resume
` [Intel-gfx] [PATCH v4 06/16] pwm: lpss: Correct get_state result for base_unit == 0
[Intel-gfx] [PATCH v1] vfio/pci: Refine Intel IGD OpRegion support
2020-07-09 17:37 UTC (5+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH 1/6] drm/i915: Add a couple of missing i915_active_fini()
2020-07-09 14:40 UTC (9+ messages)
` [Intel-gfx] [PATCH 2/6] drm/i915: Skip taking acquire mutex for no ref->active callback
` [Intel-gfx] [PATCH 3/6] drm/i915: Export a preallocate variant of i915_active_acquire()
` [Intel-gfx] [PATCH 4/6] drm/i915: Keep the most recently used active-fence upon discard
` [Intel-gfx] [PATCH 5/6] drm/i915: Make the stale cached active node available for any timeline
` [Intel-gfx] [PATCH 6/6] drm/i915: Provide a fastpath for waiting on vma bindings
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/6] drm/i915: Add a couple of missing i915_active_fini()
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [PATCH 1/2] drm/vgem: Do not allocate backing shmemfs file for an import dmabuf object
2020-07-09 14:15 UTC (16+ messages)
[Intel-gfx] [PATCH 1/4] drm/i915: Move all FBC w/as to .init_clock_gating()
2020-07-09 13:57 UTC (4+ messages)
` [Intel-gfx] [PATCH 2/4] drm/i915: Don't do WaFbcTurnOffFbcWatermark for glk
[Intel-gfx] [PATCH v7 00/17] drm/i915: Add support for HDCP 1.4 over MST
2020-07-09 12:58 UTC (19+ messages)
` [Intel-gfx] [PATCH v7 10/17] drm/i915: Support DP MST in enc_to_dig_port() function
` [Intel-gfx] [PATCH v7 11/17] drm/i915: Use ddi_update_pipe in intel_dp_mst
` [Intel-gfx] [PATCH v7 12/17] drm/i915: Factor out HDCP shim functions from dp for use by dp_mst
` [Intel-gfx] [PATCH v7 13/17] drm/i915: Plumb port through hdcp init
` [Intel-gfx] [PATCH v7 14/17] drm/i915: Add connector to hdcp_shim->check_link()
` [Intel-gfx] [PATCH v7 15/17] drm/mst: Add support for QUERY_STREAM_ENCRYPTION_STATUS MST sideband message
` [Intel-gfx] [PATCH v7 17/17] drm/i915: Add HDCP 1.4 support for MST connectors
[Intel-gfx] [PATCH 0/9] drm: Add privacy-screen class and connector properties
2020-07-09 12:48 UTC (3+ messages)
[Intel-gfx] [PATCH 1/9] drm/i915/sdvo: Reduce the size of the on stack buffers
2020-07-09 12:20 UTC (15+ messages)
` [Intel-gfx] [PATCH 4/9] drm/i915/sdvo: Fix SDVO colorimetry bit defines
` [Intel-gfx] [PATCH 5/9] drm/i915/sdvo: Implement limited color range for SDVO HDMI properly
` [Intel-gfx] [PATCH 6/9] drm/i915: Reject DRM_MODE_FLAG_DBLCLK with DVI sinks
` [Intel-gfx] [PATCH 7/9] drm/i915/sdvo: Make SDVO deal with HDMI pixel repeat
` [Intel-gfx] [PATCH 8/9] drm/i915/sdvo: Make .get_modes() return the number of modes
` [Intel-gfx] [PATCH 9/9] drm/i915/dvo: "
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