messages from 2020-07-09 19:32:28 to 2020-07-13 12:38:06 UTC [more...]
[Intel-gfx] [PATCH v4 00/15] acpi/pwm/i915: Convert pwm-crc and i915 driver's PWM code to use the atomic PWM API
2020-07-11 13:58 UTC (13+ messages)
` [Intel-gfx] [PATCH v4 06/16] pwm: lpss: Correct get_state result for base_unit == 0
` [Intel-gfx] [PATCH v4 16/16] drm/i915: panel: Use atomic PWM API for devs with an external PWM controller
[Intel-gfx] [PATCH v8 00/12] Introduce CAP_PERFMON to secure system performance monitoring and observability
2020-07-13 12:37 UTC (7+ messages)
[Intel-gfx] [PATCH] drm/i915/gt: Free stale request on destroying the virtual engine
2020-07-13 12:35 UTC (3+ messages)
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for "
[Intel-gfx] s/obj->mm.lock//
2020-07-13 12:22 UTC (19+ messages)
` [Intel-gfx] [PATCH 04/20] drm/i915/gem: Rename execbuf.bind_link to unbound_link
` [Intel-gfx] [PATCH 05/20] drm/i915/gem: Break apart the early i915_vma_pin from execbuf object lookup
` [Intel-gfx] [PATCH 09/20] drm/i915/gem: Assign context id for async work
` [Intel-gfx] [PATCH 10/20] drm/i915: Export a preallocate variant of i915_active_acquire()
[Intel-gfx] [PATCH] drm/i915/gt: Ignore irq enabling on the virtual engines
2020-07-13 10:39 UTC (5+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [PATCH] drm/i915/gt: Always reset the engine, even if inactive, on execlists failure
2020-07-13 9:34 UTC (4+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] linux-next: manual merge of the tty tree with the drm-misc tree
2020-07-13 5:24 UTC
[Intel-gfx] [RFC 00/60] DG1 LMEM enabling
2020-07-13 5:09 UTC (70+ messages)
` [Intel-gfx] [RFC 01/60] drm/i915: Add has_master_unit_irq flag
` [Intel-gfx] [RFC 02/60] drm/i915/dg1: add initial DG-1 definitions
` [Intel-gfx] [RFC 03/60] drm/i915/dg1: Add DG1 PCI IDs
` [Intel-gfx] [RFC 04/60] drm/i915/dg1: add support for the master unit interrupt
` [Intel-gfx] [RFC 05/60] drm/i915/dg1: Remove SHPD_FILTER_CNT register programming
` [Intel-gfx] [RFC 06/60] drm/i915/dg1: Add fake PCH
` [Intel-gfx] [RFC 07/60] drm/i915/dg1: Initialize RAWCLK properly
` [Intel-gfx] [RFC 08/60] drm/i915/dg1: Define MOCS table for DG1
` [Intel-gfx] [RFC 09/60] drm/i915/dg1: Add DG1 power wells
` [Intel-gfx] [RFC 10/60] drm/i915/dg1: Increase mmio size to 4MB
` [Intel-gfx] [RFC 11/60] drm/i915/dg1: Wait for pcode/uncore handshake at startup
` [Intel-gfx] [RFC 12/60] drm/i915/dg1: Add DPLL macros for DG1
` [Intel-gfx] [RFC 13/60] drm/i915/dg1: Add and setup DPLLs "
` [Intel-gfx] [RFC 14/60] drm/i915/dg1: Enable DPLL "
` [Intel-gfx] [RFC 15/60] drm/i915/dg1: add hpd interrupt handling
` [Intel-gfx] [RFC 16/60] drm/i915/dg1: invert HPD pins
` [Intel-gfx] [RFC 17/60] drm/i915/dg1: gmbus pin mapping
` [Intel-gfx] [RFC 18/60] drm/i915/dg1: Enable first 2 ports for DG1
` [Intel-gfx] [RFC 19/60] drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D
` [Intel-gfx] [RFC 20/60] drm/i915/dg1: Update comp master/slave relationships for PHYs
` [Intel-gfx] [RFC 21/60] drm/i915/dg1: Update voltage swing tables for DP
` [Intel-gfx] [RFC 22/60] drm/i915/dg1: provide port/phy mapping for vbt
` [Intel-gfx] [RFC 23/60] drm/i915/dg1: map/unmap pll clocks
` [Intel-gfx] [RFC 24/60] drm/i915/dg1: enable PORT C/D aka D/E
` [Intel-gfx] [RFC 25/60] drm/i915/dg1: Load DMC
` [Intel-gfx] [RFC 26/60] drm/i915/rkl: Add initial workarounds
` [Intel-gfx] [RFC 27/60] drm/i915/dg1: Add initial DG1 workarounds
` [Intel-gfx] [RFC 28/60] drm/i915/dg1: DG1 does not support DC6
` [Intel-gfx] [RFC 29/60] drm/i915/lmem: Limit block size to 4G
` [Intel-gfx] [RFC 30/60] drm/i915/lmem: Do not check r->sgt.pfn for NULL
` [Intel-gfx] [RFC 31/60] drm/i915/dgfx: define llc and snooping behaviour
` [Intel-gfx] [RFC 32/60] drm/i915/lmem: support pread
` [Intel-gfx] [RFC 33/60] drm/i915/lmem: support pwrite
` [Intel-gfx] [RFC 34/60] drm/i915: introduce kernel blitter_context
` [Intel-gfx] [RFC 35/60] drm/i915/query: Expose memory regions through the query uAPI
` [Intel-gfx] [RFC 36/60] drm/i915/uapi: introduce drm_i915_gem_create_ext
` [Intel-gfx] [RFC 37/60] drm/i915/lmem: allocate cmd ring in lmem
` [Intel-gfx] [RFC 38/60] drm/i915/dg1: Introduce dmabuf mmap to LMEM
` [Intel-gfx] [RFC 39/60] drm/i915: setup the LMEM region
` [Intel-gfx] [RFC 40/60] drm/i915: drop fake LMEM
` [Intel-gfx] [RFC 41/60] drm/i915: Distinction of memory regions
` [Intel-gfx] [RFC 42/60] drm/i915: PPGTT support
` [Intel-gfx] [RFC 43/60] drm/i915: support GGTT LMEM entries
` [Intel-gfx] [RFC 44/60] drm/i915: allocate context from LMEM
` [Intel-gfx] [RFC 45/60] drm/i915: move engine scratch to LMEM
` [Intel-gfx] [RFC 46/60] drm/i915: Provide a way to disable PCIe relaxed write ordering
` [Intel-gfx] [RFC 47/60] drm/i915: setup GPU device lmem region
` [Intel-gfx] [RFC 48/60] drm/i915: Fix object page offset within a region
` [Intel-gfx] [RFC 49/60] drm/i915: add i915_gem_object_is_devmem() function
` [Intel-gfx] [RFC 50/60] drm/i915: finish memory region support for stolen objects
` [Intel-gfx] [RFC 51/60] drm/i915/lmem: support optional CPU clearing for special internal use
` [Intel-gfx] [RFC 52/60] drm/i915/guc: put all guc objects in lmem when available
` [Intel-gfx] [RFC 53/60] drm/i915: Create stolen memory region from local memory
` [Intel-gfx] [RFC 54/60] drm/i915/lmem: Bypass aperture when lmem is available
` [Intel-gfx] [RFC 55/60] drm/i915/lmem: reset the lmem buffer created by fbdev
` [Intel-gfx] [RFC 56/60] drm/i915/dsb: Enable lmem for dsb
` [Intel-gfx] [RFC 57/60] drm/i915: Reintroduce mem->reserved
` [Intel-gfx] [RFC 58/60] drm/i915/dg1: Reserve first 1MB of local memory
` [Intel-gfx] [RFC 59/60] drm/i915: defer pd lmem block put to worker
` [Intel-gfx] [RFC 60/60] drm/i915/lmem: allocate HWSP in lmem
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for DG1 LMEM enabling
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] DG1 VRAM question
2020-07-13 4:45 UTC (6+ messages)
[Intel-gfx] [PATCH 00/25] dma-fence annotations, round 3
2020-07-12 22:27 UTC (13+ messages)
` [Intel-gfx] [PATCH 02/25] dma-fence: prime lockdep annotations
` [Intel-gfx] [PATCH 04/25] drm/vkms: Annotate vblank timer
[Intel-gfx] thinkpad x60: oops in eb_relocate_dma in next-20200710
2020-07-11 20:46 UTC
[Intel-gfx] [PATCH] drm/i915: Recalculate FBC w/a stride when needed
2020-07-11 10:17 UTC (5+ messages)
` [Intel-gfx] ✗ Fi.CI.BAT: failure for "
` [Intel-gfx] [PATCH v2] "
` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Recalculate FBC w/a stride when needed (rev2)
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [PATCH] drm/i915: Correct location of Wa_1408615072
2020-07-11 2:27 UTC (3+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH] drm/i915: Pull printing GT capabilities on error to err_print_gt
2020-07-11 0:54 UTC (4+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH v3 0/2] drm/probe_helper, i915: Validate MST modes against PBN limits
2020-07-10 23:21 UTC (10+ messages)
` [Intel-gfx] [PATCH v3 1/2] drm/probe_helper: Add drm_connector_helper_funcs.mode_valid_ctx
` [Intel-gfx] [PATCH v3 2/2] drm/i915/mst: filter out the display mode exceed sink's capability
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/probe_helper, i915: Validate MST modes against PBN limits (rev3)
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH] drm/i915: Be wary of data races when reading the active execlists
2020-07-10 21:03 UTC (3+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH 1/7] drm/i915/gt: Replace opencoded i915_gem_object_pin_map()
2020-07-10 17:56 UTC (4+ messages)
` [Intel-gfx] [PATCH 5/7] drm/i915: Preallocate stashes for vma page-directories
[Intel-gfx] [PATCH] drm/i915: Provide i915_request debug Kconfig options
2020-07-10 17:45 UTC (2+ messages)
` [Intel-gfx] ✗ Fi.CI.BAT: failure for "
[Intel-gfx] [bug report] drm/i915: Move the engine mask to intel_gt_info
2020-07-10 14:11 UTC
[Intel-gfx] [PATCH] drm/i915/gt: Be defensive in the face of false CS events
2020-07-10 17:23 UTC (14+ messages)
` [Intel-gfx] [PATCH v2] "
` [Intel-gfx] [PATCH v3] "
` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Be defensive in the face of false CS events (rev5)
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH v6] drm/i915: Init lspcon after HPD in intel_dp_detect()
2020-07-10 15:48 UTC (3+ messages)
[Intel-gfx] [PATCH i-g-t 1/6] lib/i915: Report unknown device as the future
2020-07-10 14:11 UTC (7+ messages)
` [Intel-gfx] [PATCH i-g-t 2/6] tools: Use the gt number stored in the device info
` [Intel-gfx] [PATCH i-g-t 3/6] lib/i915: Pick a subtest conformant name for an unknown engine
` [Intel-gfx] [PATCH i-g-t 4/6] i915/gem_close: Adapt to allow duplicate handles
` [Intel-gfx] [igt-dev] "
` [Intel-gfx] [PATCH i-g-t 5/6] i915/gem_exec_schedule: Try to spot unfairness
` [Intel-gfx] [PATCH i-g-t 6/6] i915/gem_softpin: Active rebinds
[Intel-gfx] [PATCH] drm/fb-helper: Fix vt restore
2020-07-10 13:09 UTC (4+ messages)
[Intel-gfx] [PATCH 03/25] dma-buf.rst: Document why idenfinite fences are a bad idea
2020-07-10 12:30 UTC (3+ messages)
` [Intel-gfx] [PATCH 1/2] dma-buf.rst: Document why indefinite "
[Intel-gfx] [PATCH] drm/i915: WARN if max vswing/pre-emphasis violates the DP spec
2020-07-10 12:02 UTC (3+ messages)
[Intel-gfx] [PATCH v4 1/5] drm/i915/display: Replace drm_i915_private in voltage swing functions by intel_encoder
2020-07-10 11:56 UTC (7+ messages)
` [Intel-gfx] [PATCH v4 4/5] drm/i915/display: Implement HOBL
` [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v4,1/5] drm/i915/display: Replace drm_i915_private in voltage swing functions by intel_encoder (rev2)
[Intel-gfx] [PATCH 15/25] drm/tilcdc: Use standard drm_atomic_helper_commit
2020-07-10 11:16 UTC (3+ messages)
` [Intel-gfx] [PATCH] "
[Intel-gfx] [PATCH] drm/i915/perf: Use GTT when saving/restoring engine GPR
2020-07-10 9:43 UTC (10+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH] drm/i915/selftest: Check that GPR are restored across noa_wait
2020-07-10 5:34 UTC (3+ messages)
` [Intel-gfx] ✗ Fi.CI.BAT: failure for "
[Intel-gfx] [CI 1/2] drm/i915/perf: Use GTT when saving/restoring engine GPR
2020-07-10 2:47 UTC (4+ messages)
` [Intel-gfx] [CI 2/2] drm/i915/selftest: Check that GPR are restored across noa_wait
` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/2] drm/i915/perf: Use GTT when saving/restoring engine GPR
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [CI 1/6] drm/i915: Add has_master_unit_irq flag
2020-07-10 2:40 UTC (9+ messages)
` [Intel-gfx] [CI 2/6] drm/i915/dg1: add initial DG-1 definitions
` [Intel-gfx] [CI 3/6] drm/i915/dg1: Add DG1 PCI IDs
` [Intel-gfx] [CI 4/6] drm/i915/dg1: add support for the master unit interrupt
` [Intel-gfx] [CI 5/6] drm/i915/dg1: Remove SHPD_FILTER_CNT register programming
` [Intel-gfx] [CI 6/6] drm/i915/dg1: Add fake PCH
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/6] drm/i915: Add has_master_unit_irq flag
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [CI] drm/i915/gt: Optimise aliasing-ppgtt allocations
2020-07-09 22:26 UTC (3+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [PATCH v3 03/28] drm/i915/dg1: Add DG1 PCI IDs
2020-07-09 20:56 UTC (4+ messages)
[Intel-gfx] [PATCH] drm/i915/selftests: Fix compare functions provided for sorting
2020-07-09 19:52 UTC (2+ messages)
` [Intel-gfx] ✓ Fi.CI.IGT: success for "
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