messages from 2020-10-04 15:45:16 to 2020-10-07 12:03:38 UTC [more...]
[Intel-gfx] [PATCH 1/3] drm/i915: Mark ininitial fb obj as WT on eLLC machines to avoid rcu lockup during fbdev init
2020-10-07 12:03 UTC (2+ messages)
` [Intel-gfx] [PATCH 2/3] drm/i915: Fix MOCS PTE setting for gen9+
[Intel-gfx] [PATCH] drm/i915/jsl: Split EHL/JSL platform info and PCI ids
2020-10-07 11:49 UTC (3+ messages)
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for "
[Intel-gfx] [PATCH] drm/i915/gem: Perform all asynchronous waits prior to marking payload start
2020-10-07 11:46 UTC (5+ messages)
` [Intel-gfx] ✗ Fi.CI.BAT: failure for "
[Intel-gfx] [PATCH] drm/i915/gt: Ignore dt==0 for reporting underflows
2020-10-07 11:19 UTC (2+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
[Intel-gfx] [PATCH 1/3] drm/i915: Reorder hpd init vs. display resume
2020-10-07 11:06 UTC (5+ messages)
` [Intel-gfx] [PATCH 2/3] drm/i915: Do drm_mode_config_reset() after HPD init
` [Intel-gfx] [PATCH 3/3] drm/i915: Refactor .hpd_irq_setup() calls a bit
` [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915: Reorder hpd init vs. display resume
[Intel-gfx] [PATCH] drm/i915/gt: Undo forced context restores after trivial preemptions
2020-10-07 9:30 UTC (2+ messages)
[Intel-gfx] [PATCH v2] drm/i915/gt: Track the most recent pulse for the heartbeat
2020-10-07 8:40 UTC (3+ messages)
` [Intel-gfx] [PATCH v3] "
[Intel-gfx] [PATCH rdma-next v5 0/4] Dynamicaly allocate SG table from the pages
2020-10-07 8:15 UTC (5+ messages)
` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Dynamicaly allocate SG table from the pages (rev3)
[Intel-gfx] [PATCH 1/2] drm/i915/dpcd_bl: Skip testing control capability with force DPCD quirk
2020-10-07 6:58 UTC
[Intel-gfx] [CI 1/8] drm/i915/dg1: add more PCI ids
2020-10-07 2:21 UTC (11+ messages)
` [Intel-gfx] [CI 2/8] drm/i915/dg1: Initialize RAWCLK properly
` [Intel-gfx] [CI 3/8] drm/i915/dg1: Define MOCS table for DG1
` [Intel-gfx] [CI 4/8] drm/i915/dg1: Increase mmio size to 4MB
` [Intel-gfx] [CI 5/8] drm/i915/dg1: gmbus pin mapping
` [Intel-gfx] [CI 6/8] drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D
` [Intel-gfx] [CI 7/8] drm/i915/dg1: Update comp master/slave relationships for PHYs
` [Intel-gfx] [CI 8/8] drm/i915/dg1: provide port/phy mapping for vbt
` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,1/8] drm/i915/dg1: add more PCI ids
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH v4 1/2] drm/i915/jsl: Split EHL/JSL platform info and PCI ids
2020-10-06 22:59 UTC
[Intel-gfx] [PATCH v3 0/2] drm/i915/jsl: Update JSL Voltage swing table
2020-10-06 22:23 UTC (4+ messages)
` [Intel-gfx] [PATCH v3 1/2] drm/i915/jsl: Split EHL/JSL platform info and PCI ids
[Intel-gfx] [PATCH 00/20] drm/i915: Futher cleanup around hpd pins and port identfiers
2020-10-06 21:52 UTC (30+ messages)
` [Intel-gfx] [PATCH 01/20] drm/i915: Sort the mess around ICP TC hotplugs regs
` [Intel-gfx] [PATCH 02/20] drm/i915: s/PORT_TC/TC_PORT_TC/
` [Intel-gfx] [PATCH 03/20] drm/i915: Add PORT_TCn aliases to enum port
` [Intel-gfx] [PATCH 04/20] drm/i915: Give DDI encoders even better names
` [Intel-gfx] [PATCH 05/20] drm/i915: Introduce AUX_CH_USBCn
` [Intel-gfx] [PATCH 06/20] drm/i915: Pimp AUX CH names
` [Intel-gfx] [PATCH 07/20] drm/i915: Use AUX_CH_USBCn for the RKL VBT AUX CH setup
` [Intel-gfx] [PATCH 08/20] drm/i915: Parametrize BXT_DE_PORT_HP_DDI with hpd_pin
` [Intel-gfx] [PATCH v2 "
` [Intel-gfx] [PATCH 09/20] drm/i915: Introduce GEN8_DE_PORT_HOTPLUG()
` [Intel-gfx] [PATCH v2 "
` [Intel-gfx] [PATCH 10/20] drm/i915: s/port/hpd_pin/ for icp+ ddi hpd bits
` [Intel-gfx] [PATCH 11/20] drm/i915: s/tc_port/hpd_pin/ in GEN11_{TC, TBT}_HOTPLUG()
` [Intel-gfx] [PATCH 12/20] drm/i915: s/tc_port/hpd_pin/ in icp+ TC hotplug bits
` [Intel-gfx] [PATCH 13/20] drm/i915: Relocate intel_hpd_{enabled, hotplug}_irqs()
` [Intel-gfx] [PATCH 14/20] drm/i915: Split gen11_hpd_detection_setup() into tc vs. tbt variants
` [Intel-gfx] [PATCH 15/20] drm/i915: Don't enable hpd detection logic from irq_postinstall()
` [Intel-gfx] [PATCH 16/20] drm/i915: Rename 'tmp_mask'
` [Intel-gfx] [PATCH 17/20] drm/i915: Remove the per-plaform IIR HPD masking
` [Intel-gfx] [PATCH 18/20] drm/i915: Enable hpd logic only for ports that are present
` [Intel-gfx] [PATCH 19/20] drm/i915: Use GEN3_IRQ_INIT() to init south interrupts in icp+
` [Intel-gfx] [PATCH 20/20] drm/i915: Get rid of ibx_irq_pre_postinstall()
` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Futher cleanup around hpd pins and port identfiers
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Futher cleanup around hpd pins and port identfiers (rev3)
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [PATCH] ALSA: hda/i915 - fix list corruption with concurrent probes
2020-10-06 21:02 UTC (3+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [PATCH] drm/i915/ehl: Remove require_force_probe protection
2020-10-06 20:12 UTC (7+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [v7 00/10] Enable HDR on MCA LSPCON based Gen9 devices
2020-10-06 19:27 UTC (14+ messages)
` [Intel-gfx] [v7 01/10] drm/i915/display: Add HDR Capability detection for LSPCON
` [Intel-gfx] [v7 02/10] drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon
` [Intel-gfx] [v7 03/10] drm/i915/display: Attach HDR property for capable Gen9 devices
` [Intel-gfx] [v7 04/10] drm/i915/display: Enable BT2020 for HDR on LSPCON devices
` [Intel-gfx] [v7 05/10] drm/i915/display: Enable HDR for Parade based lspcon
` [Intel-gfx] [v7 06/10] drm/i915/display: Implement infoframes readback for LSPCON
` [Intel-gfx] [v7 07/10] drm/i915/display: Implement DRM infoframe read "
` [Intel-gfx] [v7 08/10] drm/i915/lspcon: Create separate infoframe_enabled helper
` [Intel-gfx] [v7 09/10] drm/i915/lspcon: Do not send DRM infoframes to non-HDMI sinks
` [Intel-gfx] [v7 10/10] drm/i915/display: [NOT FOR MERGE] Reduce blanking to support 4k60@10bpp for LSPCON
` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable HDR on MCA LSPCON based Gen9 devices (rev7)
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [PATCH] drm/i915/gt: Track the most recent pulse for the heartbeat
2020-10-06 18:39 UTC (3+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Track the most recent pulse for the heartbeat (rev3)
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [PATCH v2 1/6] drm/i915: Shut down displays gracefully on reboot
2020-10-06 18:33 UTC (16+ messages)
` [Intel-gfx] [PATCH v2 2/6] drm/i915: Add an encoder .shutdown() hook
` [Intel-gfx] [PATCH v2 3/6] drm/i915: Replace the VLV/CHV eDP reboot notifier with the "
` [Intel-gfx] [PATCH v2 4/6] drm/i915: Wait for eDP panel power cycle delay on reboot on all platforms
` [Intel-gfx] [PATCH v2 5/6] drm/i915: Wait for LVDS panel power cycle delay on reboot
` [Intel-gfx] [PATCH v2 6/6] drm/i915: Wait for VLV/CHV/BXT/GLK DSI "
[Intel-gfx] [PATCH v2 1/3] drm/i915/vbt: Fix backlight parsing for VBT 234+
2020-10-06 17:10 UTC (3+ messages)
[Intel-gfx] [RESEND] Requests For Proposals for hosting XDC2021 are now open
2020-10-06 8:48 UTC (2+ messages)
` [Intel-gfx] [Freedreno] "
[Intel-gfx] [PATCH v5 44/52] docs: gpu: i915.rst: Fix several C duplication warnings
2020-10-06 14:03 UTC
[Intel-gfx] [PATCH 1/3] drm/i915/cnl: Handle incorrect divider values during WRPLL HW readout
2020-10-06 14:55 UTC (4+ messages)
` [Intel-gfx] [PATCH 2/3] drm/i915/skl: Move sanity check of WRPLL p1 divider value next to its read-out
` [Intel-gfx] [PATCH 3/3] drm/i915/skl: Fix WRPLL p0/1/2 PDIV divider selection
` [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915/cnl: Handle incorrect divider values during WRPLL HW readout
[Intel-gfx] [RFC 0/8] Add support for DP-HDMI2.1 PCON
2020-10-06 14:22 UTC (10+ messages)
` [Intel-gfx] [RFC 1/8] drm/edid: Add additional HFVSDB fields for HDMI2.1
` [Intel-gfx] [RFC 2/8] drm/edid: Parse MAX_FRL field from HFVSDB block
` [Intel-gfx] [RFC 3/8] drm/dp_helper: Add FRL training support for a DP-HDMI2.1 PCON
` [Intel-gfx] [RFC 4/8] drm/i915: Capture max frl rate for PCON in dfp cap structure
` [Intel-gfx] [RFC 5/8] drm/i915: Add support for starting FRL training for HDMI2.1 via PCON
` [Intel-gfx] [RFC 6/8] drm/i915: Check for FRL training before DP Link training
` [Intel-gfx] [RFC 7/8] drm/dp_helper: Add support for link status and link recovery
` [Intel-gfx] [RFC 8/8] drm/i915: Add support for enabling link status and recovery
` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Add support for DP-HDMI2.1 PCON (rev2)
[Intel-gfx] [v6 00/11] Enable HDR on MCA LSPCON based Gen9 devices
2020-10-06 12:27 UTC (23+ messages)
` [Intel-gfx] [v6 02/11] drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon
` [Intel-gfx] [v6 03/11] drm/i915/display: Attach HDR property for capable Gen9 devices
` [Intel-gfx] [v6 04/11] drm/i915/display: Enable BT2020 for HDR on LSPCON devices
` [Intel-gfx] [v6 05/11] drm/i915/display: Enable HDR for Parade based lspcon
` [Intel-gfx] [v6 06/11] drm/i915/display: Implement infoframes readback for LSPCON
` [Intel-gfx] [v6 07/11] drm/i915/display: Implement DRM infoframe read "
[Intel-gfx] [CI 1/2] drm/i915: Fix DMA mapped scatterlist walks
2020-10-06 11:09 UTC (4+ messages)
` [Intel-gfx] [CI 2/2] drm/i915: Fix DMA mapped scatterlist lookup
` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/2] drm/i915: Fix DMA mapped scatterlist walks
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] linux-next: manual merge of the extcon tree with the drm-misc tree
2020-10-06 10:58 UTC (3+ messages)
[Intel-gfx] [PATCH 0/5] drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock
2020-10-06 11:04 UTC (29+ messages)
` [Intel-gfx] [PATCH 1/5] drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programming
` [Intel-gfx] [PATCH v3 "
` [Intel-gfx] [PATCH 3/5] drm/i915: Check for unsupported DP link rates during initial commit
` [Intel-gfx] [PATCH 4/5] drm/i915: Add an encoder hook to sanitize its state during init/resume
` [Intel-gfx] [PATCH v2 "
` [Intel-gfx] [PATCH v3 "
` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev6)
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev7)
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev6)
` [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev7)
[Intel-gfx] [PATCH] drm/i915/gt: Scrub HW state on remove
2020-10-06 10:35 UTC (2+ messages)
[Intel-gfx] [PATCH 2/5] drm/i915: Move the initial fastset commit check to encoder hooks
2020-10-06 10:05 UTC (9+ messages)
` [Intel-gfx] [PATCH v2 "
` [Intel-gfx] [PATCH v3 "
[Intel-gfx] [PATCH 2/2] drm/i915: Fix DMA mapped scatterlist lookup
2020-10-06 9:27 UTC (4+ messages)
` [Intel-gfx] [PATCH v2] "
[Intel-gfx] [PATCH] drm/i915: Rename i915_{save,restore}_state()
2020-10-06 9:03 UTC (5+ messages)
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for "
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✓ Fi.CI.IGT: "
` [Intel-gfx] [PATCH] drm/i915: Rename i915_{save, restore}_state()
[Intel-gfx] [PATCH] drm/i915/tgl/psr: Fix glitches when doing frontbuffer modifications
2020-10-05 21:48 UTC (5+ messages)
` [Intel-gfx] ✗ Fi.CI.IGT: failure for "
` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl/psr: Fix glitches when doing frontbuffer modifications (rev2)
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [CI 1/2] drm/i915: don't conflate is_dgfx with fake lmem
2020-10-05 22:52 UTC (3+ messages)
` [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [CI,1/2] "
[Intel-gfx] [PATCH 0/2] Gen12 forcewake and multicast updates
2020-10-05 23:38 UTC (3+ messages)
` [Intel-gfx] [PATCH 1/2] drm/i915: Update gen12 forcewake table
[Intel-gfx] [PATCH CI] drm/i915/display/ehl: Limit eDP to HBR2
2020-10-05 22:58 UTC (3+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display/ehl: Limit eDP to HBR2 (rev4)
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH v4 0/2] drm/i915/jsl: Update JSL Voltage swing table
2020-10-05 22:51 UTC (7+ messages)
` [Intel-gfx] [PATCH v4 1/2] drm/i915/jsl: Split EHL/JSL platform info and PCI ids
` [Intel-gfx] [PATCH v4 2/2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/jsl: Update JSL Voltage swing table
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH v4 0/2] drm/i915/jsl: Update JSL Voltage swing table
2020-10-05 20:40 UTC (5+ messages)
` [Intel-gfx] [PATCH v4 1/2] drm/i915/jsl: Split EHL/JSL platform info and PCI ids
` [Intel-gfx] [PATCH v4 2/2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2
` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/jsl: Update JSL Voltage swing table
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [RFC] drm/i915/gt: reduce context clear batch size to avoid gpu hang
2020-10-05 12:04 UTC (2+ messages)
` [Intel-gfx] ✗ Fi.CI.BUILD: failure for "
[Intel-gfx] [PATCH] drm/i915: Implement display WA #1142:kbl, cfl, cml
2020-10-05 8:00 UTC (4+ messages)
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