messages from 2021-01-12 20:10:08 to 2021-01-14 10:55:05 UTC [more...]
[Intel-gfx] [PULL] drm-intel-fixes
2021-01-14 10:54 UTC
[Intel-gfx] [PATCH] drm/i915: support two CSC module on gen11 and later
2021-01-14 10:45 UTC (2+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
[Intel-gfx] [PATCH v2 1/2] drm/i915/selftests: Exercise relative mmio paths to non-privileged registers
2021-01-14 10:38 UTC (2+ messages)
` [Intel-gfx] [PATCH v2 2/2] drm/i915/selftests: Exercise cross-process context isolation
[Intel-gfx] [PATCH] drm/i915/selftests: fix the uint*_t types that have crept in
2021-01-14 10:23 UTC (5+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [PATCH 1/2] drm/i915/selftests: Exercise relative mmio paths to non-privileged registers
2021-01-14 10:18 UTC (4+ messages)
` [Intel-gfx] [PATCH 2/2] drm/i915/selftests: Exercise cross-process context isolation
[Intel-gfx] [CI] drm/i915/gt: Reapply ppgtt enabling after engine resets
2021-01-14 10:14 UTC
[Intel-gfx] [PATCH] drm/i915/selftests: Exercise relative mmio paths to non-privileged registers
2021-01-14 10:10 UTC (2+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
[Intel-gfx] [rfc v7] rebased refactor of intel_display
2021-01-14 10:08 UTC (13+ messages)
` [Intel-gfx] [PATCH 01/11] drm/i915: refactor some crtc code out of intel display. (v2)
` [Intel-gfx] [PATCH 02/11] drm/i915: refactor pll code out into intel_dpll.c
` [Intel-gfx] [PATCH 03/11] drm/i915: split fdi code out from intel_display.c
` [Intel-gfx] [PATCH 04/11] drm/i915: refactor ddi translations into a separate file
` [Intel-gfx] [PATCH 05/11] drm/i915: migrate hsw fdi code to new file
` [Intel-gfx] [PATCH 06/11] drm/i915: migrate skl planes code new file (v3)
` [Intel-gfx] [PATCH 07/11] drm/i915: move pipe update code into crtc
` [Intel-gfx] [PATCH 08/11] drm/i915: split fb scalable checks into g4x and skl versions
` [Intel-gfx] [PATCH 09/11] drm/i915: move is_ccs_modifier to an inline
` [Intel-gfx] [PATCH 10/11] drm/i915: migrate pll enable/disable code to intel_dpll.[ch]
` [Intel-gfx] [PATCH 11/11] drm/i915: migrate i9xx plane get config
` [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [01/11] drm/i915: refactor some crtc code out of intel display. (v2)
[Intel-gfx] [PATCH] drm-buf: Add debug option
2021-01-14 9:47 UTC (12+ messages)
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for "
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [PATCH v6 0/4] drm/i915: Add support for Intel's eDP backlight controls
2021-01-14 9:46 UTC (8+ messages)
` [Intel-gfx] [PATCH v6 1/4] drm/i915: Keep track of pwm-related backlight hooks separately
` [Intel-gfx] [PATCH v6 2/4] drm/i915/dp: Enable Intel's HDR backlight interface (only SDR for now)
` [Intel-gfx] [PATCH v6 3/4] drm/i915/dp: Allow forcing specific interfaces through enable_dpcd_backlight
` [Intel-gfx] [PATCH v6 4/4] drm/dp: Revert "drm/dp: Introduce EDID-based quirks"
` [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Add support for Intel's eDP backlight controls (rev9)
[Intel-gfx] [PATCH v2 00/17] drm/i915/dp: split out pps and aux
2021-01-14 8:56 UTC (21+ messages)
` [Intel-gfx] [PATCH v2 01/17] drm/i915/pps: abstract panel power sequencer from intel_dp.c
` [Intel-gfx] [PATCH v2 04/17] drm/i915/pps: rename intel_edp_panel_* to intel_pps_*
` [Intel-gfx] [PATCH v2 05/17] drm/i915/pps: rename edp_panel_* to intel_pps_*_unlocked
` [Intel-gfx] [PATCH v2 06/17] drm/i915/pps: abstract intel_pps_vdd_off_sync
` [Intel-gfx] [PATCH v2 13/17] drm/i915/pps: rename intel_dp_init_panel_power_sequencer* functions
` [Intel-gfx] [PATCH v2 14/17] drm/i915/pps: refactor init abstractions
` [Intel-gfx] [PATCH v2 15/17] drm/i915/pps: move pps code over from intel_display.c and refactor
` [Intel-gfx] [PATCH v2 16/17] drm/i915/dp: abstract struct intel_dp pps members to a sub-struct
[Intel-gfx] [PATCH] drm/i915/display: fix the uint*_t types that have crept in
2021-01-14 8:13 UTC (5+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [PATCH] drm/i915/display: remove useless use of inline
2021-01-14 8:12 UTC (5+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH] drm/i915: Only enable DFP 4:4:4->4:2:0 conversion when outputting YCbCr 4:4:4
2021-01-14 7:27 UTC (2+ messages)
[Intel-gfx] [PATCH v2] drm/i915: Try to guess PCH type even without ISA bridge
2021-01-14 5:14 UTC (4+ messages)
` [Intel-gfx] [PATCH v3] "
` [Intel-gfx] [PATCH v4] "
[Intel-gfx] [PATCH 1/2] mm/dmapool: Use might_alloc()
2021-01-14 5:07 UTC (6+ messages)
` [Intel-gfx] [PATCH 2/2] bdi: "
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] mm/dmapool: "
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Try to guess PCH type even without ISA bridge
2021-01-14 4:59 UTC (5+ messages)
` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Try to guess PCH type even without ISA bridge (rev3)
` [Intel-gfx] ✗ Fi.CI.BAT: failure "
` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Try to guess PCH type even without ISA bridge (rev4)
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH] drm/i915/uc: Add function to define defaults for GuC/HuC enable
2021-01-14 4:08 UTC (3+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/uc: Add function to define defaults for GuC/HuC enable (rev2)
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [PATCH 01/10] drm/i915: Mark up protected uses of 'i915_request_completed'
2021-01-14 3:03 UTC (23+ messages)
` [Intel-gfx] [PATCH 02/10] drm/i915: Drop i915_request.lock serialisation around await_start
` [Intel-gfx] [PATCH 03/10] drm/i915/gem: Reduce ctx->engine_mutex for reading the clone source
` [Intel-gfx] [PATCH 04/10] drm/i915/gem: Reduce ctx->engines_mutex for get_engines()
` [Intel-gfx] [PATCH 05/10] drm/i915: Reduce test_and_set_bit to set_bit in i915_request_submit()
` [Intel-gfx] [PATCH 06/10] drm/i915/gt: Drop atomic for engine->fw_active tracking
` [Intel-gfx] [PATCH 07/10] drm/i915/gt: Extract busy-stats for ring-scheduler
` [Intel-gfx] [PATCH 08/10] drm/i915/gt: Convert stats.active to plain unsigned int
` [Intel-gfx] [PATCH 09/10] drm/i915/gt: Reduce engine runtime stats from seqlock to a latch
` [Intel-gfx] [PATCH 10/10] drm/i915/gt: Reduce GT "
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/10] drm/i915: Mark up protected uses of 'i915_request_completed'
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [rfc v7] rebased refactor of intel_display
2021-01-14 3:05 UTC
[Intel-gfx] [CI 1/2] drm/i915/selftests: Force a failed engine reset
2021-01-14 2:38 UTC (10+ messages)
` [Intel-gfx] [CI 2/2] drm/i915/selftests: Bump the scheduling error threshold for fast heartbeats
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/2] drm/i915/selftests: Force a failed engine reset
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✗ Fi.CI.BAT: failure "
` [Intel-gfx] [PATCH] "
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with drm/i915/selftests: Force a failed engine reset (rev2)
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [CI] drm/i915/gt: Replace open-coded intel_engine_stop_cs()
2021-01-14 1:46 UTC (3+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Replace open-coded intel_engine_stop_cs() (rev3)
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [CI 1/2] drm/i915/gt: Rearrange vlv workarounds
2021-01-14 0:52 UTC (3+ messages)
` [Intel-gfx] [CI 2/2] drm/i915/gt: Rearrange ivb workarounds
` [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/2] drm/i915/gt: Rearrange vlv workarounds
[Intel-gfx] [PATCH] drm/i915/gt: Prune inlines
2021-01-14 0:51 UTC (4+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] linux-next: build failure after merge of the drm-misc tree
2021-01-14 0:31 UTC
[Intel-gfx] [PATCH] drm/i915/gt: Prune 'inline' from execlists
2021-01-14 0:01 UTC (3+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [PATCH v4 00/18] VRR/Adaptive Sync Enabling on DP/eDP for TGL+
2021-01-13 23:05 UTC (22+ messages)
` [Intel-gfx] [PATCH v4 01/18] drm/i915/display/vrr: Create VRR file and add VRR capability check
` [Intel-gfx] [PATCH v4 02/18] drm/i915/display/dp: Attach and set drm connector VRR property
` [Intel-gfx] [PATCH v4 03/18] drm/i915: Store framestart_delay in dev_priv
` [Intel-gfx] [PATCH v4 04/18] drm/i915: Extract intel_mode_vblank_start()
` [Intel-gfx] [PATCH v4 05/18] drm/i915: Extract intel_crtc_scanlines_since_frame_timestamp()
` [Intel-gfx] [PATCH v4 06/18] drm/i915/display/dp: Compute VRR state in atomic_check
` [Intel-gfx] [PATCH v4 07/18] drm/i915/display/dp: Do not enable PSR if VRR is enabled
` [Intel-gfx] [PATCH v4 08/18] drm/i915/display: VRR + DRRS cannot be enabled together
` [Intel-gfx] [PATCH v4 09/18] drm/i915: Rename VRR_CTL reg fields
` [Intel-gfx] [PATCH v4 10/18] drm/i915/display/vrr: Configure and enable VRR in modeset enable
` [Intel-gfx] [PATCH v4 11/18] drm/i915/display/vrr: Send VRR push to flip the frame
` [Intel-gfx] [PATCH v4 12/18] drm/i915/display/vrr: Disable VRR in modeset disable path
` [Intel-gfx] [PATCH v4 13/18] drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP Sink
` [Intel-gfx] [PATCH v4 14/18] drm/i915/display: Add HW state readout for VRR
` [Intel-gfx] [PATCH v4 15/18] drm/i915/display: Helpers for VRR vblank min and max start
` [Intel-gfx] [PATCH v4 16/18] drm/i915: Add vrr state dump
` [Intel-gfx] [PATCH v4 17/18] drm/i915: Fix vblank timestamps with VRR
` [Intel-gfx] [PATCH v4 18/18] drm/i915: Fix vblank evasion with vrr
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for VRR/Adaptive Sync Enabling on DP/eDP for TGL+
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✗ Fi.CI.BAT: failure "
[Intel-gfx] [PATCH] drm/i915/hdcp: Disable the QSES check for HDCP 1.4 over MST
2021-01-13 20:45 UTC (6+ messages)
[Intel-gfx] [PATCH] drm/i915/dg1: Apply WA 1409120013 and 14011059788
2021-01-13 20:03 UTC (4+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH] drm/i915/selftests: Bump the scheduling threshold for fast heartbeats
2021-01-13 19:04 UTC (9+ messages)
` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/selftests: Bump the scheduling threshold for fast heartbeats (rev2)
` [Intel-gfx] [PATCH v2] drm/i915/selftests: Bump the scheduling error threshold for fast heartbeats
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Bump the scheduling threshold for fast heartbeats (rev3)
` [Intel-gfx] ✗ Fi.CI.BAT: failure "
[Intel-gfx] [PATCH] drm/i915/dp: DPTX writes Swing/Pre-emphs(DPCD 0x103-0x106) requested during PHY Layer testing
2021-01-13 15:04 UTC (2+ messages)
[Intel-gfx] [PATCH] drm/i915/display: Bitwise or the conversion colour specifier together
2021-01-13 11:52 UTC (5+ messages)
[Intel-gfx] [PATCH] drm/i915/selftests: Rearrange ktime_get to reduce latency against CS
2021-01-13 10:52 UTC (4+ messages)
[Intel-gfx] [PATCH] drm/i915/lmem: make intel_region_lmem_ops static
2021-01-13 10:16 UTC (6+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [PATCH v9 00/19] HDCP 2.2 and HDCP 1.4 Gen12 DP MST support
2021-01-13 3:40 UTC (3+ messages)
` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (rev9)
[Intel-gfx] [PATCH v2 0/4]
2021-01-13 2:17 UTC (6+ messages)
` [Intel-gfx] [PATCH v2 1/4] drm/i915/guc: Delete GuC code unused in future patches
` [Intel-gfx] [PATCH v2 2/4] drm/i915/guc: do not dump execlists state with GuC submission
` [Intel-gfx] [PATCH v2 3/4] drm/i915/guc: init engine directly in GuC submission mode
` [Intel-gfx] [PATCH v2 4/4] drm/i915/guc: stop calling execlists_set_default_submission
` [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [v2,1/4] drm/i915/guc: Delete GuC code unused in future patches
[Intel-gfx] [PATCH] drm/i915/region: make intel_region_map static
2021-01-13 1:54 UTC (2+ messages)
` [Intel-gfx] ✗ Fi.CI.IGT: failure for "
[Intel-gfx] [PATCH 0/5] Split GuC submission from execlists submission
2021-01-13 1:03 UTC (8+ messages)
` [Intel-gfx] [PATCH 2/5] drm/i915/guc: do not dump execlists state with GuC submission
[Intel-gfx] [PATCH 00/22] Introduce Alderlake-S
2021-01-12 23:47 UTC (3+ messages)
` [Intel-gfx] [PATCH 09/22] drm/i915/adl_s: Configure Port clock registers for ADL-S
[Intel-gfx] [PATCH v2] drm/i915/debugfs : PM_REQ and PM_RES registers
2021-01-12 21:40 UTC (2+ messages)
` [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/debugfs : PM_REQ and PM_RES registers (rev2)
[Intel-gfx] [PATCH 1/2] drm/i915/dp: Move intel_dp_set_signal_levels() to intel_dp_link_training.c
2021-01-12 21:21 UTC (5+ messages)
` [Intel-gfx] [PATCH 2/2] drm/i915/dp: Fix LTTPR vswing/pre-emp setting in non-transparent mode
[Intel-gfx] [PATCH] drm/i915: move region_lmem under gt
2021-01-12 21:08 UTC (2+ messages)
[Intel-gfx] [PATCH] drm/i915/selftests: Force a failed engine reset
2021-01-12 20:43 UTC (3+ messages)
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