messages from 2022-03-29 08:49:46 to 2022-03-30 15:22:57 UTC [more...]
[Intel-gfx] [PATCH 1/2] drm/i915/audio: unify audio codec enable/disable debug logging
2022-03-30 15:22 UTC (7+ messages)
` [Intel-gfx] [PATCH 2/2] drm/i915/audio: move has_audio checks to within codec enable/disable
` [Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [1/2] drm/i915/audio: unify audio codec enable/disable debug logging
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [RESEND 1/3] drm/i915/dmc: abstract GPU error state dump
2022-03-30 15:22 UTC (5+ messages)
` [Intel-gfx] [RESEND 2/3] drm/i915/dmc: hide DMC version macros
` [Intel-gfx] [RESEND 3/3] drm/i915/dmc: split out dmc registers to a separate file
` [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [RESEND,1/3] drm/i915/dmc: abstract GPU error state dump
[Intel-gfx] [PATCH 00/12] drm/edid: cleanup and refactoring around validity checks
2022-03-30 15:16 UTC (19+ messages)
` [Intel-gfx] [PATCH 01/12] drm/edid: use struct edid * in drm_do_get_edid()
` [Intel-gfx] [PATCH 02/12] drm/edid: clean up EDID block checksum functions
` [Intel-gfx] [PATCH 03/12] drm/edid: add edid_block_tag() helper to get the EDID extension tag
` [Intel-gfx] [PATCH 04/12] drm/edid: make drm_edid_header_is_valid() accept void pointer
` [Intel-gfx] [PATCH 05/12] drm/edid: clean up edid_is_zero()
` [Intel-gfx] [PATCH 06/12] drm/edid: split out edid_header_fix()
` [Intel-gfx] [PATCH 07/12] drm/edid: split drm_edid_block_valid() to check and act parts
` [Intel-gfx] [PATCH 08/12] drm/edid: use a better variable name for EDID block read retries
` [Intel-gfx] [PATCH 09/12] drm/edid: simplify block check when filtering invalid blocks
` [Intel-gfx] [PATCH 10/12] drm/edid: split out invalid block filtering to a separate function
` [Intel-gfx] [PATCH 11/12] drm/edid: track invalid blocks in drm_do_get_edid()
` [Intel-gfx] [PATCH 12/12] drm/edid: reduce magic when updating the EDID block checksum
` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/edid: cleanup and refactoring around validity checks
` [Intel-gfx] ✗ Fi.CI.DOCS: "
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH CI 1/4] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL
2022-03-30 14:38 UTC (5+ messages)
` [Intel-gfx] [PATCH CI 2/4] drm/i915/display/adlp: Adjust MBUS DBOX BW and B credits
` [Intel-gfx] [PATCH CI 3/4] drm/i915/display: Add HAS_MBUS_JOINING
` [Intel-gfx] [PATCH CI 4/4] drm/i915/display/adlp: Fix programing of PIPE_MBUS_DBOX_CTL
` [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [CI,1/4] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL
[Intel-gfx] [PATCH] drm/i915/dp: make DSC usage logging actually useful
2022-03-30 13:27 UTC (5+ messages)
` [Intel-gfx] ✗ Fi.CI.DOCS: warning for "
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [RFC v2 0/2] drm/doc/rfc: i915 VM_BIND feature design + uapi
2022-03-30 12:51 UTC (3+ messages)
` [Intel-gfx] [RFC v2 2/2] drm/doc/rfc: VM_BIND uapi definition
[Intel-gfx] [PATCH 1/3] drm/i915/dmc: abstract GPU error state dump
2022-03-30 12:14 UTC (4+ messages)
` [Intel-gfx] [PATCH 2/3] drm/i915/dmc: hide DMC version macros
` [Intel-gfx] [PATCH 3/3] drm/i915/dmc: split out dmc registers to a separate file
` [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/3] drm/i915/dmc: abstract GPU error state dump
[Intel-gfx] [PATCH] drm: round_up the size to the alignment value
2022-03-30 11:38 UTC (8+ messages)
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for "
` [Intel-gfx] ✗ Fi.CI.DOCS: "
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH v4 1/4] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL
2022-03-30 10:59 UTC (12+ messages)
` [Intel-gfx] [PATCH v4 2/4] drm/i915/display/adlp: Adjust MBUS DBOX BW and B credits
` [Intel-gfx] [PATCH v4 3/4] drm/i915/display: Add HAS_MBUS_JOINING
` [Intel-gfx] [PATCH v4 4/4] drm/i915/display/adlp: Fix programing of PIPE_MBUS_DBOX_CTL
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v4,1/4] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✗ Fi.CI.DOCS: "
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH v3 0/2] Splitting intel-gtt calls for non-x86 platforms
2022-03-30 10:23 UTC (7+ messages)
` [Intel-gfx] [PATCH v3 1/2] drm/i915/gt: Split intel-gtt functions by arch
` [Intel-gfx] [PATCH v3 2/2] drm/i915: Require INTEL_GTT to depend on X86
` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Splitting intel-gtt calls for non-x86 platforms (rev3)
[Intel-gfx] [PATCH] drm/i915/display/: Refactor hsw_crtc_enable for bigjoiner cleanup
2022-03-30 9:53 UTC (6+ messages)
[Intel-gfx] [PATCH v2 0/2] Splitting intel-gtt calls for non-x86 platforms
2022-03-30 9:44 UTC (5+ messages)
` [Intel-gfx] [PATCH v2 1/2] drm/i915/gt: Split intel-gtt functions by arch
` [Intel-gfx] [PATCH v2 2/2] drm/i915: Require INTEL_GTT to depend on X86
` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Splitting intel-gtt calls for non-x86 platforms (rev2)
[Intel-gfx] [PATCH] drm/i915/gt: fix i915_reg_t initialization
2022-03-30 9:31 UTC (3+ messages)
[Intel-gfx] [PATCH v2] drm: add a check to verify the size alignment
2022-03-30 9:17 UTC (6+ messages)
[Intel-gfx] [PATCH v11] drm/amdgpu: add drm buddy support to amdgpu
2022-03-30 6:53 UTC (7+ messages)
[Intel-gfx] [PATCH 1/2] drm/i915/display/psr: Set partial frame enable when forcing full frame fetch
2022-03-30 6:23 UTC (5+ messages)
` [Intel-gfx] [PATCH 2/2] drm/i915/display/psr: Use continuos full frame to handle frontbuffer invalidations
[Intel-gfx] [PATCH 00/13] drm/i915: Start reordering modeset clock calculations
2022-03-30 3:37 UTC (10+ messages)
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Start reordering modeset clock calculations (rev2)
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✗ Fi.CI.DOCS: "
` [Intel-gfx] ✗ Fi.CI.BAT: failure "
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Start reordering modeset clock calculations (rev3)
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✗ Fi.CI.DOCS: "
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [PATCH] drm/i915/dg2: Add Wa_22014226127
2022-03-29 23:16 UTC (11+ messages)
` [Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/dg2: Add Wa_22014226127 (rev4)
` [Intel-gfx] ✗ Fi.CI.BAT: failure "
` [Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/dg2: Add Wa_22014226127 (rev5)
` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dg2: Add Wa_22014226127
` [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dg2: Add Wa_22014226127 (rev5)
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/dg2: Add Wa_22014226127 (rev6)
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [PATCH] drm/i915/debugfs: Dump i915 children runtime status
2022-03-29 23:09 UTC (3+ messages)
[Intel-gfx] [PATCH] drm/i915/hwconfig: Add DG2 support
2022-03-29 22:49 UTC (2+ messages)
[Intel-gfx] [PATCH v3 1/3] drm/i915/display: Program PIPE_MBUS_DBOX_CTL with adl-p values
2022-03-29 21:23 UTC (6+ messages)
` [Intel-gfx] [PATCH v3 3/3] drm/i915/display/adlp: Fix programing of PIPE_MBUS_DBOX_CTL
[Intel-gfx] [drm-tip:drm-tip 4/8] drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c:200:33: error: no member named 'tbo' in 'struct ttm_range_mgr_node'
2022-03-29 20:50 UTC
[Intel-gfx] [PATCH 1/2] drm/i915/ats-m: add ATS-M platform info
2022-03-29 20:35 UTC (6+ messages)
` [Intel-gfx] [PATCH 2/2] topic/core-for-CI: Add ATS-M PCI IDs
` [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/ats-m: add ATS-M platform info
[Intel-gfx] [drm-tip:drm-tip 4/8] drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c:200:45: error: 'struct ttm_range_mgr_node' has no member named 'tbo'
2022-03-29 20:09 UTC
[Intel-gfx] [PATCH] [topic/core-for-CI] Revert "drm/i915/dg2: Add relocation exception"
2022-03-29 19:50 UTC (4+ messages)
` [Intel-gfx] ✗ Fi.CI.BAT: failure for Revert "drm/i915/dg2: Add relocation exception" (rev2)
[Intel-gfx] [PATCH v3 00/18] drm/i915: Refactor the display power domain mappings
2022-03-29 18:32 UTC (23+ messages)
` [Intel-gfx] [PATCH v3 01/18] drm/i915: Move per-platform power well hooks to intel_display_power_well.c
` [Intel-gfx] [PATCH v3 02/18] drm/i915: Unexport the for_each_power_well() macros
` [Intel-gfx] [PATCH v3 03/18] drm/i915: Move the power domain->well mappings to intel_display_power_map.c
` [Intel-gfx] [PATCH v3 04/18] drm/i915: Move the dg2 fixed_enable_delay power well param to a common bitfield
` [Intel-gfx] [PATCH v3 05/18] drm/i915: Move the HSW power well flags "
` [Intel-gfx] [PATCH v3 06/18] drm/i915: Rename the power domain names to end with pipes/ports
` [Intel-gfx] [PATCH v3 07/18] drm/i915: Sanitize the power well names
` [Intel-gfx] [PATCH v3 08/18] drm/i915: Convert the power well descriptor domain mask to an array of domains
` [Intel-gfx] [PATCH v3 09/18] drm/i915: Convert the u64 power well domains mask to a bitmap
` [Intel-gfx] [PATCH v3 10/18] drm/i915: Simplify power well definitions by adding power well instances
` [Intel-gfx] [PATCH v3 11/18] drm/i915: Allow platforms to share power well descriptors
` [Intel-gfx] [PATCH v3 12/18] drm/i915: Simplify the DG1 "
` [Intel-gfx] [PATCH v3 13/18] drm/i915: Sanitize the ADL-S power well definition
` [Intel-gfx] [PATCH v3 14/18] drm/i915: Sanitize the port -> DDI/AUX power domain mapping for each platform
` [Intel-gfx] [PATCH v3 15/18] drm/i915: Remove the aliasing of power domain enum values
` [Intel-gfx] [PATCH v3 16/18] drm/i915: Remove the ICL specific TBT power domains
` [Intel-gfx] [PATCH v3 17/18] drm/i915: Remove duplicate DDI/AUX power domain mappings
` [Intel-gfx] [PATCH v3 18/18] drm/i915: Remove the XELPD specific AUX and DDI power domains
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Refactor the display power domain mappings (rev3)
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✗ Fi.CI.DOCS: "
` [Intel-gfx] ✗ Fi.CI.BAT: failure "
[Intel-gfx] [CI 0/6] Add driver for GSC controller
2022-03-29 17:48 UTC (5+ messages)
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add driver for GSC controller (rev13)
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✗ Fi.CI.DOCS: "
` [Intel-gfx] ✗ Fi.CI.BAT: failure "
[Intel-gfx] [PATCH 00/11] drm/i915: Finish off static DRRS
2022-03-29 17:08 UTC (13+ messages)
` [Intel-gfx] [PATCH 01/11] drm/i915: Extract intel_edp_has_drrs()
` [Intel-gfx] [PATCH 02/11] drm/i915: Put fixed modes directly onto the panel's fixed_modes list
` [Intel-gfx] [PATCH 03/11] drm/i915: Refactor non-EDID fixed mode duplication
` [Intel-gfx] [PATCH 04/11] drm/i915: Nuke intel_drrs_init()
` [Intel-gfx] [PATCH 05/11] drm/i915: Combine the EDID fixed_mode+downclock_mode lookup into one
` [Intel-gfx] [PATCH 06/11] drm/i915: Stop duplicating the EDID fixed/downclock modes
` [Intel-gfx] [PATCH 07/11] drm/i915: Allow an arbitrary number of downclock modes
` [Intel-gfx] [PATCH 08/11] drm/i915: Allow higher refresh rate alternate fixed modes
` [Intel-gfx] [PATCH 09/11] drm/i915: Move intel_drrs_compute_config() into intel_dp.c
` [Intel-gfx] [PATCH 10/11] drm/i915: Allow static DRRS on all eDP ports
` [Intel-gfx] [PATCH 11/11] drm/i915: Allow static DRRS on LVDS
` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Finish off static DRRS
[Intel-gfx] [PATCH] drm/i915/adlp: Fix register corruption after DDI clock enabling
2022-03-29 16:43 UTC (4+ messages)
` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/adlp: Fix register corruption after DDI clock enabling (rev2)
` [Intel-gfx] ✗ Fi.CI.DOCS: "
` [Intel-gfx] ✗ Fi.CI.BAT: failure "
[Intel-gfx] [PATCH] drm/i915: avoid concurrent writes to aux_inv
2022-03-29 15:59 UTC (4+ messages)
` [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: avoid concurrent writes to aux_inv (rev10)
[Intel-gfx] [PATCH 22/23] drm/i915: drop bo->moving dependency
2022-03-29 15:57 UTC (2+ messages)
[Intel-gfx] [PATCH] drm/i915: Add RPL-S PCI IDs
2022-03-29 14:57 UTC (5+ messages)
[Intel-gfx] [PATCH] drm/i915/adl_p: Increase CDCLK by 15% if PSR2 is used
2022-03-29 13:53 UTC (7+ messages)
[Intel-gfx] [CI v2] drm/i915: Move intel_vtd_active and run_as_guest to i915_utils
2022-03-29 13:33 UTC (6+ messages)
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Move intel_vtd_active and run_as_guest to i915_utils (rev2)
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✗ Fi.CI.DOCS: "
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH v7 0/9] drm/i915/ttm: Evict and restore of compressed object
2022-03-29 13:23 UTC (3+ messages)
` [Intel-gfx] [PATCH v7 3/9] drm/i915/gt: Optimize the migration and clear loop
[Intel-gfx] [PATCH] docs: gpu: i915.rst: Fix DRRS documentation
2022-03-29 13:13 UTC (3+ messages)
` [Intel-gfx] ✓ Fi.CI.IGT: success for docs: gpu: i915.rst: Fix DRRS documentation (rev2)
[Intel-gfx] [PATCH 1/2] dma-buf/sync-file: fix logic error in new fence merge code
2022-03-29 13:10 UTC (8+ messages)
` [Intel-gfx] [PATCH 2/2] dma-buf: handle empty dma_fence_arrays gracefully
` [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] dma-buf/sync-file: fix logic error in new fence merge code
[Intel-gfx] [PATCH v3 00/12] drm/edid: constify EDID parsing, with fixes
2022-03-29 12:55 UTC (6+ messages)
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/edid: constify EDID parsing, with fixes (rev3)
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✗ Fi.CI.DOCS: "
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [CI 1/4] drm/i915/gt: Explicitly clear BB_OFFSET for new contexts
2022-03-29 11:16 UTC (5+ messages)
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/4] drm/i915/gt: Explicitly clear BB_OFFSET for new contexts (rev2)
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✗ Fi.CI.DOCS: "
` [Intel-gfx] ✗ Fi.CI.BAT: failure "
[Intel-gfx] [bug report] High refresh rates broken on eDP display with Optimus
2022-03-29 10:34 UTC (2+ messages)
[Intel-gfx] [PATCH 0/4] drm/i915: Optimize CSC updates for ilk+
2022-03-29 9:29 UTC (9+ messages)
` [Intel-gfx] [PATCH 1/4] drm/i915: Remove locks around skl+ scaler programming
` [Intel-gfx] [PATCH 2/4] drm/i915: Make ilk+ pfit regiser unlocked
` [Intel-gfx] [PATCH 3/4] drm/i915: Split color_commit() into noarm+arm pair
` [Intel-gfx] [PATCH 4/4] drm/i915: Split pipe+output CSC programming to "
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