messages from 2023-08-23 10:17:47 to 2023-08-24 10:41:52 UTC [more...]
[Intel-gfx] [PATCH] drm/i915/rpl: Add new RPL PCI-IDs
2023-08-24 10:41 UTC (4+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
[Intel-gfx] [PATCH] drm/i915/display/vrr: Compute VRR min/max based on highest clock mode for DRRS panel
2023-08-24 10:39 UTC (5+ messages)
` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for "
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [PATCH v2 00/22] drm/i915: Improve BW management on shared display links
2023-08-24 10:37 UTC (29+ messages)
` [Intel-gfx] [PATCH v2 01/22] drm/i915/dp: Factor out helpers to compute the link limits
` [Intel-gfx] [PATCH v2 02/22] drm/i915/dp: Track the pipe and link bpp limits separately
` [Intel-gfx] [PATCH v2 03/22] drm/i915/dp: Skip computing a non-DSC link config if DSC is needed
` [Intel-gfx] [PATCH v2 04/22] drm/i915/dp: Update the link bpp limits for DSC mode
` [Intel-gfx] [PATCH v2 05/22] drm/i915/dp: Limit the output link bpp in "
` [Intel-gfx] [PATCH v2 06/22] drm/i915: Add helper to modeset a set of pipes
` [Intel-gfx] [PATCH v2 07/22] drm/i915: Factor out a helper to check/compute all the CRTC states
` [Intel-gfx] [PATCH v2 08/22] drm/i915/fdi: Improve FDI BW sharing between pipe B and C
` [Intel-gfx] [PATCH v2 09/22] drm/dp_mst: Fix fractional bpp scaling in drm_dp_calc_pbn_mode()
` [Intel-gfx] [PATCH v2 10/22] drm/dp_mst: Add a way to calculate PBN values with FEC overhead
` [Intel-gfx] [PATCH v2 11/22] drm/dp_mst: Add helper to determine if an MST port is downstream of another port
` [Intel-gfx] [PATCH v2 12/22] drm/dp_mst: Factor out a helper to check the atomic state of a topology manager
` [Intel-gfx] [PATCH v2 13/22] drm/dp_mst: Swap the order of checking root vs. non-root port BW limitations
` [Intel-gfx] [PATCH v2 14/22] drm/i915/dp_mst: Fix PBN calculation with FEC overhead
` [Intel-gfx] [PATCH v2 15/22] drm/i915/dp_mst: Add atomic state for all streams on pre-tgl platforms
` [Intel-gfx] [PATCH v2 16/22] drm/i915/dp_mst: Program the DSC PPS SDP for each stream
` [Intel-gfx] [PATCH v2 17/22] drm/i915/dp: Make sure the DSC PPS SDP is disabled whenever DSC is disabled
` [Intel-gfx] [PATCH v2 18/22] drm/i915/dp_mst: Enable DSC decompression if any stream needs this
` [Intel-gfx] [PATCH v2 19/22] drm/i915/dp_mst: Add missing DSC compression disabling
` [Intel-gfx] [PATCH v2 20/22] drm/i915/dp_mst: Allow DSC only for sink ports of the first branch device
` [Intel-gfx] [PATCH v2 21/22] drm/i915/dp_mst: Improve BW sharing between MST streams
` [Intel-gfx] [PATCH v2 22/22] drm/i915/dp_mst: Check BW limitations only after all streams are computed
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Improve BW management on shared display links (rev2)
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✓ Fi.CI.BAT: success "
[Intel-gfx] [PATCH 00/42] Enable Lunar Lake display
2023-08-24 10:34 UTC (73+ messages)
` [Intel-gfx] [PATCH 01/42] drm/i915: Start using plane scale factor for relative data rate
` [Intel-gfx] [PATCH 02/42] drm/i915/display: Remove unused POWER_DOMAIN_MASK
` [Intel-gfx] [PATCH 03/42] drm/i915/cx0: Add intel_cx0_get_owned_lane_mask()
` [Intel-gfx] [PATCH 04/42] drm/i915: Simplify intel_cx0_program_phy_lane() with loop
` [Intel-gfx] [PATCH 05/42] drm/i915/cx0: Enable/disable TX only for owned PHY lanes
` [Intel-gfx] [PATCH 06/42] drm/i915/cx0: Program vswing only for owned lanes
` [Intel-gfx] [PATCH 07/42] drm/i915/tc: rename mtl_tc_port_get_pin_assignment_mask()
` [Intel-gfx] [PATCH 08/42] drm/i915/tc: make intel_tc_port_get_lane_mask() static
` [Intel-gfx] [PATCH 09/42] drm/i915/tc: move legacy code out of the main _max_lane_count() func
` [Intel-gfx] [PATCH 10/42] drm/i915/tc: remove "fia" from intel_tc_port_fia_max_lane_count()
` [Intel-gfx] [PATCH 11/42] drm/xe/lnl: Add IS_LUNARLAKE
` [Intel-gfx] [Intel-xe] "
` [Intel-gfx] [PATCH 12/42] drm/i915/lnl: Add display definitions
` [Intel-gfx] [Intel-xe] "
` [Intel-gfx] [PATCH 13/42] drm/i915: Re-order if/else ladder in intel_detect_pch()
` [Intel-gfx] [Intel-xe] "
` [Intel-gfx] [PATCH 14/42] drm/i915/lnl: Add fake PCH
` [Intel-gfx] [Intel-xe] "
` [Intel-gfx] [PATCH 15/42] drm/i915/xe2lpd: Treat cursor plane as regular plane for DDB allocation
` [Intel-gfx] [Intel-xe] "
` [Intel-gfx] [PATCH 16/42] drm/i915/xe2lpd: Move D2D enable/disable
` [Intel-gfx] [Intel-xe] "
` [Intel-gfx] [PATCH 17/42] drm/i915/xe2lpd: D2D Enable preserve bits in DDI_BUF_CTL
` [Intel-gfx] [Intel-xe] "
` [Intel-gfx] [PATCH 18/42] drm/i915/xe2lpd: Move registers to PICA
` [Intel-gfx] [Intel-xe] "
` [Intel-gfx] [PATCH 19/42] drm/i915/xe2lpd: Don't try to program PLANE_AUX_DIST
` [Intel-gfx] [PATCH 20/42] drm/i915/xe2lpd: Register DE_RRMR has been removed
` [Intel-gfx] [Intel-xe] "
` [Intel-gfx] [PATCH 21/42] drm/i915/xe2lpd: Add display power well
` [Intel-gfx] [Intel-xe] "
` [Intel-gfx] [PATCH 22/42] drm/i915/xe2lpd: Add DC state support
` [Intel-gfx] [PATCH 23/42] drm/i915/xe2lpd: FBC is now supported on all pipes
` [Intel-gfx] [Intel-xe] "
` [Intel-gfx] [PATCH 24/42] drm/i915/display: Remove FBC capability from fused off pipes
` [Intel-gfx] [Intel-xe] "
` [Intel-gfx] [PATCH 25/42] drm/i915/xe2lpd: Add support for DP aux channels
` [Intel-gfx] [Intel-xe] "
` [Intel-gfx] [PATCH 26/42] drm/i915/xe2lpd: Handle port AUX interrupts
` [Intel-gfx] [Intel-xe] "
` [Intel-gfx] [PATCH 27/42] drm/i915/xe2lpd: Read pin assignment from IOM
` [Intel-gfx] [Intel-xe] "
` [Intel-gfx] [PATCH 28/42] drm/i915/xe2lpd: enable odd size and panning for planar yuv on xe2lpd
` [Intel-gfx] [PATCH 29/42] drm/i915/xe2lpd: Add support for HPD
` [Intel-gfx] [Intel-xe] "
` [Intel-gfx] [PATCH 30/42] drm/i915/xe2lpd: Extend Wa_15010685871
` [Intel-gfx] [Intel-xe] "
` [Intel-gfx] [PATCH 31/42] drm/i915/lnl: Add gmbus/ddc support
` [Intel-gfx] [Intel-xe] "
` [Intel-gfx] [PATCH 32/42] drm/i915/lnl: Introduce MDCLK
` [Intel-gfx] [Intel-xe] "
` [Intel-gfx] [PATCH 33/42] drm/i915/lnl: Add CDCLK table
` [Intel-gfx] [Intel-xe] "
` [Intel-gfx] [PATCH 34/42] drm/i915/lnl: Start using CDCLK through PLL
` [Intel-gfx] [Intel-xe] "
` [Intel-gfx] [PATCH 35/42] drm/i915/lnl: Introduce MDCLK_CDCLK ratio to DBuf
` [Intel-gfx] [PATCH 36/42] drm/i915/lnl: Add support for CDCLK initialization sequence
` [Intel-gfx] [PATCH 37/42] drm/i915/xe2lpd: Write DBuf after CDCLK change in post plane
` [Intel-gfx] [PATCH 38/42] drm/i915/lnl: Serialize global state if mdclk/cdclk ratio changes
` [Intel-gfx] [PATCH 39/42] drm/i915/lnl: Add pll table for LNL platform
` [Intel-gfx] [PATCH 40/42] drm/i915/lnl: Add support to check c10 phy link rate
` [Intel-gfx] [PATCH 41/42] drm/i915/xe2lpd: Update mbus on post plane updates
` [Intel-gfx] [PATCH 42/42] drm/xe/lnl: Enable the display support
` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Enable Lunar Lake display
[Intel-gfx] [PATCH] drm/i915/display: add lock while printing frontbuffer tracking bits to debugfs
2023-08-24 10:06 UTC (3+ messages)
[Intel-gfx] [PATCH v2 0/4] HDCP MST aux issue fix
2023-08-24 10:07 UTC (4+ messages)
` [Intel-gfx] [PATCH v2 2/4] drm/i915/hdcp: Propagate aux info in DP HDCP functions
` [Intel-gfx] ✗ Fi.CI.IGT: failure for HDCP MST aux issue fix (rev3)
[Intel-gfx] [PATCH 0/3] Define a final failure state when link training fails
2023-08-24 9:56 UTC (10+ messages)
` [Intel-gfx] [PATCH v2 0/6] drm/i915/dp_link_training: "
` [Intel-gfx] [PATCH v2 1/6] drm/i915/dp_link_training: Add a final failing state to link training fallback
` [Intel-gfx] [PATCH v2 2/6] drm/i915/dp_link_training: Add a final failing state to link training fallback for MST
` [Intel-gfx] [PATCH v2 3/6] drm/dp_mst: Add drm_dp_set_mst_topology_link_status()
` [Intel-gfx] [PATCH v2 4/6] drm/i915: Move DP modeset_retry_work into intel_dp
` [Intel-gfx] [PATCH v2 5/6] drm/i915/dp_link_training: Set all downstream MST ports to BAD before retrying
` [Intel-gfx] [PATCH v2 6/6] drm/i915/dp_link_training: Emit a link-status=Bad uevent with trigger property
` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Define a final failure state when link training fails
[Intel-gfx] [PATCH 0/2] eDP DSC fixes
2023-08-24 9:45 UTC (14+ messages)
` [Intel-gfx] [PATCH 1/2] drm/display/dp: Default 8 bpc support when DSC is supported
` [Intel-gfx] [PATCH 2/2] drivers/drm/i915: Honor limits->max_bpp while computing DSC max input bpp
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for eDP DSC fixes
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✗ Fi.CI.BAT: failure "
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for eDP DSC fixes (rev2)
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✓ Fi.CI.BAT: success "
[Intel-gfx] [PULL] drm-misc-fixes
2023-08-24 8:41 UTC
[Intel-gfx] [PATCH v3 0/4] drm/i915/tc: some clean-ups in max lane count handling code
2023-08-24 7:51 UTC (11+ messages)
` [Intel-gfx] [PATCH v3 1/4] drm/i915/tc: rename mtl_tc_port_get_pin_assignment_mask()
` [Intel-gfx] [PATCH v3 4/4] drm/i915/tc: remove "fia" from intel_tc_port_fia_max_lane_count()
[Intel-gfx] [PATCH v3] drm/i915/rpl: Update pci ids for RPL P/U
2023-08-24 7:37 UTC (4+ messages)
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/rpl: Update pci ids for RPL P/U (rev3)
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✓ Fi.CI.BAT: success "
[Intel-gfx] [PATCH v2] drm/i915/rpl: Update pci ids for RPL P/U
2023-08-24 7:08 UTC (2+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/rpl: Update pci ids for RPL P/U (rev2)
[Intel-gfx] [PATCH] drm/i915: Add missing CCS documentation
2023-08-24 6:51 UTC (6+ messages)
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for "
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH v4 0/6] Panel replay phase1 implementation
2023-08-24 5:20 UTC (10+ messages)
` [Intel-gfx] [PATCH v4 1/6] drm/panelreplay: dpcd register definition for panelreplay
` [Intel-gfx] [PATCH v4 2/6] drm/i915/panelreplay: Added HAS_PANEL_REPLAY() macro
` [Intel-gfx] [PATCH v4 3/6] drm/i915/psr: Move psr specific dpcd init into own function
` [Intel-gfx] [PATCH v4 4/6] drm/i915/panelreplay: Initializaton and compute config for panel replay
` [Intel-gfx] [PATCH v4 5/6] drm/i915/panelreplay: Enable panel replay dpcd initialization for DP
` [Intel-gfx] [PATCH v4 6/6] drm/i915/panelreplay: enable/disable panel replay
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Panel replay phase1 implementation (rev6)
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✓ Fi.CI.BAT: success "
[Intel-gfx] [PATCH v2 0/2] Apply Wa_16018031267 / Wa_16018063123
2023-08-23 21:30 UTC (6+ messages)
` [Intel-gfx] [PATCH v2 1/2] drm/i915: Add WABB blit for "
` [Intel-gfx] [PATCH v2 2/2] drm/i915: Set copy engine arbitration "
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Apply Wa_16018031267 / Wa_16018063123 (rev2)
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✗ Fi.CI.BAT: failure "
[Intel-gfx] [PATCH v11 0/8] Add DSC PPS readout
2023-08-23 21:25 UTC (13+ messages)
` [Intel-gfx] [PATCH v11 1/8] drm/i915/vdsc: Refactor dsc register field macro
` [Intel-gfx] [PATCH v11 2/8] drm/i915/vdsc: Add a check for dsc split cases
` [Intel-gfx] [PATCH v11 3/8] drm/i915/vdsc: Add func to get no. of vdsc instances per pipe
` [Intel-gfx] [PATCH v11 4/8] drm/i915/vdsc: Add function to read any PPS register
` [Intel-gfx] [PATCH v11 5/8] drm/i915/vdsc: Add function to write in "
` [Intel-gfx] [PATCH v11 6/8] drm/i915/vdsc: Remove unused dsc registers
` [Intel-gfx] [PATCH v11 7/8] drm/i915/vdsc: Fill the intel_dsc_get_pps_config function
` [Intel-gfx] [PATCH v11 8/8] drm/i915/display: Compare the readout dsc pps params
` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add DSC PPS readout (rev11)
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [REGRESSION] HDMI connector detection broken in 6.3 on Intel(R) Celeron(R) N3060 integrated graphics
2023-08-23 19:30 UTC (8+ messages)
[Intel-gfx] [PATCH 0/2] Apply Wa_16018031267 / Wa_16018063123
2023-08-23 18:45 UTC (3+ messages)
` [Intel-gfx] [PATCH 1/2] drm/i915: Add WABB blit for "
` [Intel-gfx] [PATCH 2/2] drm/i915: Set copy engine arbitration for pipeblit WA
[Intel-gfx] PR for GSC FW release 102.0.0.1655 for MTL
2023-08-23 18:42 UTC
[Intel-gfx] [PATCH v5] drm/i915: Avoid circular locking dependency when flush delayed work on gt reset
2023-08-23 17:37 UTC (4+ messages)
[Intel-gfx] [PATCH] drm/i915/mtl: Adding DeviceID for Arrowlake-S under MTL
2023-08-23 15:10 UTC (3+ messages)
` [Intel-gfx] ✗ Fi.CI.IGT: failure for "
[Intel-gfx] [CI 1/2] drm: Add an HPD poll helper to reschedule the poll work
2023-08-23 14:27 UTC (3+ messages)
` [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [CI,1/2] drm: Add an HPD poll helper to reschedule the poll work (rev2)
[Intel-gfx] [PATCH v6 0/4] drm: Use full allocated minor range for DRM
2023-08-23 14:06 UTC (10+ messages)
` [Intel-gfx] [PATCH v6 3/4] drm: Expand max DRM device number to full MINORBITS
[Intel-gfx] [PATCH v1 0/2] SDP split for DP-MST
2023-08-23 13:10 UTC (2+ messages)
` [Intel-gfx] ✓ Fi.CI.IGT: success for SDP split for DP-MST (rev3)
[Intel-gfx] [PATCH] drm/i915/vma: constify unbind_fence_ops
2023-08-23 12:27 UTC (2+ messages)
[Intel-gfx] [PATCH 0/4] drm/amd/display: stop using drm_edid_override_connector_update()
2023-08-23 10:43 UTC (2+ messages)
` [Intel-gfx] ✓ Fi.CI.IGT: success for drm/amd/display: stop using drm_edid_override_connector_update() (rev2)
[Intel-gfx] [PATCH v9 0/8] Add DSC PPS readout
2023-08-23 10:17 UTC (3+ messages)
` [Intel-gfx] [PATCH v9 4/8] drm/i915/vdsc: Add function to read any PPS register
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