messages from 2024-04-03 09:00:32 to 2024-04-05 01:51:31 UTC [more...]
[PATCH v2 00/17] drm/i915: Bigjoiner modeset sequence redesign and MST support
2024-04-05 1:51 UTC (24+ messages)
` [PATCH v2 01/17] drm/i915: Update pipes in reverse order for bigjoiner
` [PATCH v2 02/17] drm/i915/psr: Disable PSR when bigjoiner is used
` [PATCH v2 03/17] drm/i915: Disable port sync "
` [PATCH v2 04/17] drm/i915: Disable live M/N updates when using bigjoiner
` [PATCH v2 05/17] drm/i915/vrr: Disable VRR "
` [PATCH v2 06/17] drm/i915: Fix intel_modeset_pipe_config_late() for bigjoiner
` [PATCH v2 07/17] drm/i915: s/intel_dp_can_bigjoiner()/intel_dp_has_bigjoiner()/
` [PATCH v2 08/17] drm/i915: Extract intel_dp_joiner_needs_dsc()
` [PATCH v2 09/17] drm/i915/mst: Check intel_dp_joiner_needs_dsc()
` [PATCH v2 10/17] drm/i915: Pass connector to intel_dp_need_bigjoiner()
` [PATCH v2 11/17] drm/i915: Introduce intel_crtc_joined_pipe_mask()
` [PATCH v2 12/17] drm/i915: Extract intel_ddi_post_disable_hdmi_or_sst()
` [PATCH v2 13/17] drm/i915: Utilize intel_crtc_joined_pipe_mask() more
` [PATCH v2 14/17] drm/i915: Handle joined pipes inside hsw_crtc_disable()
` [PATCH v2 15/17] drm/i915: Handle joined pipes inside hsw_crtc_enable()
` [PATCH v2 16/17] drm/i915/mst: Add bigjoiner handling to MST modeset sequence
` [PATCH v2 17/17] drm/i915: Allow bigjoiner for MST
` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Bigjoiner modeset sequence redesign and MST support (rev2)
` ✗ Fi.CI.SPARSE: "
` ✗ Fi.CI.BAT: failure "
` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Bigjoiner modeset sequence redesign and MST support (rev3)
` ✗ Fi.CI.SPARSE: "
` ✓ Fi.CI.BAT: success "
v6.8 stable backport request for drm/i915
2024-04-04 21:25 UTC (3+ messages)
[PATCH 00/12] drm/client: Use after free and debug improvements
2024-04-04 21:22 UTC (16+ messages)
` [PATCH 01/12] drm/client: Fully protect modes[] with dev->mode_config.mutex
` [PATCH 02/12] drm/client: s/drm_connector_has_preferred_mode/drm_connector_preferred_mode/
` [PATCH 03/12] drm/client: Use drm_mode_destroy()
` [PATCH 04/12] drm/client: Add a FIXME around crtc->mode usage
` [PATCH 05/12] drm/client: Nuke outdated fastboot comment
` [PATCH 06/12] drm/client: Constify modes
` [PATCH 07/12] drm/client: Use array notation for function arguments
` [PATCH 08/12] drm/client: Extract drm_connector_first_mode()
` [PATCH 09/12] drm/client: Switch to per-device debugs
` [PATCH 10/12] drm/client: Use [CONNECTOR:%d:%s] formatting
` [PATCH 11/12] drm/client: Streamline mode selection debugs
` [PATCH 12/12] drm/probe-helper: Switch to per-device debugs
` ✗ Fi.CI.CHECKPATCH: warning for drm/client: Use after free and debug improvements
` ✗ Fi.CI.SPARSE: "
` ✓ Fi.CI.BAT: success "
[PULL] drm-intel-fixes
2024-04-04 17:45 UTC
[linux-next:master] BUILD REGRESSION 2b3d5988ae2cb5cd945ddbc653f0a71706231fdd
2024-04-04 17:31 UTC
[PATCH v5] drm/i915: limit eDP MSO pipe only for display version 20 and below
2024-04-04 17:04 UTC (2+ messages)
` ✗ Fi.CI.BAT: failure for drm/i915: limit eDP MSO pipe only for display version 20 and below (rev3)
[PATCH v17 0/9] Enable Adaptive Sync SDP Support for DP
2024-04-04 14:59 UTC (4+ messages)
[PULL] drm-xe-fixes
2024-04-04 14:49 UTC
[PATCH 0/7] Enable Aux Based EDP HDR
2024-04-04 10:15 UTC (14+ messages)
` [PATCH 1/7] drm/i915/dp: Make has_gamut_metadata_dip() non static
` [PATCH 2/7] drm/i915/dp: Add TCON HDR capability checks
` [PATCH 3/7] drm/i915/dp: Fix Register bit naming
` [PATCH 4/7] drm/i915/dp: Fix comments on EDP HDR DPCD registers
` [PATCH 5/7] drm/i915/dp: Enable AUX based backlight for HDR
` [PATCH 6/7] drm/i915/dp: Write panel override luminance values
` [PATCH 7/7] drm/i915/dp: Limit brightness level to 20
` ✗ Fi.CI.SPARSE: warning for Enable Aux Based EDP HDR
` ✓ Fi.CI.BAT: success "
` ✗ Fi.CI.IGT: failure "
[PATCH v4 0/4] drm/i915/display: DMC wakelock implementation
2024-04-04 12:39 UTC (8+ messages)
` [PATCH v4 1/4] drm/i915/display: add support for DMC wakelocks
` [PATCH v4 2/4] drm/i915/display: don't allow DMC wakelock on older hardware
` [PATCH v4 3/4] drm/i915/display: add module parameter to enable DMC wakelock
` [PATCH v4 4/4] drm/i915/display: tie DMC wakelock to DC5/6 state transitions
` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: DMC wakelock implementation (rev4)
` ✗ Fi.CI.SPARSE: "
` ✓ Fi.CI.BAT: success "
[rebase 1/3] drm: Add drm_vblank_work_flush_all()
2024-04-04 11:34 UTC (6+ messages)
` [rebase 2/3] drm/i915: Use vblank worker to unpin old legacy cursor fb safely
` [rebase 3/3] drm/i915: Use the same vblank worker for atomic unpin
` ✗ Fi.CI.CHECKPATCH: warning for series starting with [rebase,1/3] drm: Add drm_vblank_work_flush_all()
` ✗ Fi.CI.SPARSE: "
` ✓ Fi.CI.BAT: success "
[PULL] drm-misc-fixes
2024-04-04 10:48 UTC
[PATCH v3 0/4] drm/i915/display: DMC wakelock implementation
2024-04-04 10:03 UTC (10+ messages)
` [PATCH v3 2/4] drm/i915/display: don't allow DMC wakelock on older hardware
` [PATCH v3 3/4] drm/i915/display: add module parameter to enable DMC wakelock
` [PATCH v3 4/4] drm/i915/display: tie DMC wakelock to DC5/6 state transitions
[PATCH v2 00/14] drm/i915: Implemnt vblank sycnhronized mbus joining changes
2024-04-04 7:31 UTC (4+ messages)
` ✗ Fi.CI.SPARSE: warning for drm/i915: Implemnt vblank sycnhronized mbus joining changes (rev4)
` ✓ Fi.CI.BAT: success "
` ✗ Fi.CI.IGT: failure "
[PATCH v2 00/25] Enable dislay support for Battlemage
2024-04-04 3:58 UTC (52+ messages)
` [PATCH v2 01/25] drm/i915/display: Prepare to handle new C20 PLL register address
` [PATCH v2 02/25] drm/xe/bmg: Add BMG platform definition
` [PATCH v2 03/25] drm/xe/bmg: Define IS_BATTLEMAGE macro
` [PATCH v2 04/25] drm/i915/bmg: "
` [PATCH v2 05/25] drm/i915/xe2: Skip CCS modifiers for Xe2 platforms
` [PATCH v2 06/25] drm/i915/xe2hpd: Initial cdclk table
` [PATCH v2 07/25] Revert "drm/i915/dgfx: DGFX uses direct VBT pin mapping"
` [PATCH v2 08/25] drm/i915/bmg: Extend DG2 tc check to future
` [PATCH v2 09/25] drm/i915/xe2hpd: Properly disable power in port A
` [PATCH v2 10/25] drm/i915/xe2hpd: Add new C20 PLL register address
` [PATCH v2 11/25] drm/i915/xe2hpd: Add support for eDP PLL configuration
` [PATCH v2 12/25] drm/i915/xe2hpd: update pll values in sync with Bspec
` [PATCH v2 13/25] drm/i915/xe2hpd: Add display info
` [PATCH v2 14/25] drm/i915/xe2hpd: Add missing chicken bit register programming
` [PATCH v2 15/25] drm/xe/display: Lane reversal requires writes to both context lanes
` [PATCH v2 16/25] drm/xe/xe2hpd: Define a new DRAM type INTEL_DRAM_GDDR
` [PATCH v2 17/25] drm/i915/xe2hpd: Add max memory bandwidth algorithm
` [PATCH v2 18/25] drm/i915/display: Enable RM timeout detection
` [PATCH v2 19/25] drm/i915/xe2hpd: Do not program MBUS_DBOX BW credits
` [PATCH v2 20/25] drm/i915/bmg: BMG should re-use MTL's south display logic
` [PATCH v2 21/25] drm/i915/xe2hpd: Set maximum DP rate to UHBR13.5
` [PATCH v2 22/25] drm/xe/gt_print: add xe_gt_err_once()
` [PATCH v2 23/25] drm/xe/device: implement transient flush
` [PATCH v2 24/25] drm/i915/display: perform "
` [PATCH v2 25/25] drm/xe/bmg: Enable the display support
` ✗ Fi.CI.CHECKPATCH: warning for Enable dislay support for Battlemage (rev2)
` ✗ Fi.CI.SPARSE: "
` ✓ Fi.CI.BAT: success "
` ✗ Fi.CI.IGT: failure "
[PATCH] drm/i915/guc: Fix the fix for reset lock confusion
2024-04-03 21:50 UTC (3+ messages)
[PATCH] drm/xe/display: fix potential overflow when multiplying 2 u32
2024-04-03 18:56 UTC (4+ messages)
[PATCH] drm/i915/guc: Remove bogus null check
2024-04-03 18:46 UTC (6+ messages)
[PATCH v5 00/19] Panel replay selective update support
2024-04-03 16:33 UTC (24+ messages)
` [PATCH v5 01/19] drm/i915/psr: Add some documentation of variables used in psr code
` [PATCH v5 02/19] drm/i915/psr: Set intel_crtc_state->has_psr on panel replay as well
` [PATCH v5 03/19] drm/i915/psr: Intel_psr_pause/resume needs to support panel replay
` [PATCH v5 04/19] drm/i915/psr: Do not update phy power state in case of non-eDP "
` [PATCH v5 05/19] drm/i915/psr: Check possible errors for panel replay as well
` [PATCH v5 06/19] drm/i915/psr: Do not write registers/bits not applicable for panel replay
` [PATCH v5 07/19] drm/i915/psr: Call intel_psr_init_dpcd in intel_dp_detect
` [PATCH v5 08/19] drm/i915/psr: Unify panel replay enable/disable sink
` [PATCH v5 09/19] drm/i915/psr: Panel replay has to be enabled before link training
` [PATCH v5 10/19] drm/i915/psr: Rename has_psr2 as has_sel_update
` [PATCH v5 11/19] drm/i915/psr: Rename psr2_enabled as sel_update_enabled
` [PATCH v5 12/19] drm/panelreplay: dpcd register definition for panelreplay SU
` [PATCH v5 13/19] drm/i915/psr: Detect panel replay selective update support
` [PATCH v5 14/19] drm/i915/psr: Modify intel_dp_get_su_granularity to support panel replay
` [PATCH v5 15/19] drm/i915/psr: Panel replay uses SRD_STATUS to track it's status
` [PATCH v5 16/19] drm/i915/psr: Do not apply workarounds in case of panel replay
` [PATCH v5 17/19] drm/i915/psr: Update PSR module parameter descriptions
` [PATCH v5 18/19] drm/i915/psr: Split intel_psr2_config_valid for panel replay
` [PATCH v5 19/19] drm/i915/psr: Add panel replay sel update support to debugfs interface
` ✗ Fi.CI.CHECKPATCH: warning for Panel replay selective update support (rev5)
` ✗ Fi.CI.SPARSE: "
` ✓ Fi.CI.BAT: success "
` ✗ Fi.CI.IGT: failure "
[linux-next:master] BUILD REGRESSION 727900b675b749c40ba1f6669c7ae5eb7eb8e837
2024-04-03 15:56 UTC
[PATCH 00/13] drm/i915: Implemnt vblank sycnhronized mbus joining changes
2024-04-03 15:51 UTC (4+ messages)
` [PATCH 01/13] drm/i915/cdclk: Fix CDCLK programming order when pipes are active
[PATCHv3] drm/xe/display: check for error on drmm_mutex_init
2024-04-03 15:49 UTC (2+ messages)
` ✗ Fi.CI.BAT: failure for drm/xe/display: check for error on drmm_mutex_init (rev4)
[PATCHv2] drm/xe/display: check for error on drmm_mutex_init
2024-04-03 15:32 UTC (4+ messages)
[PATCH v4] drm/i915: limit eDP MSO pipe only for display version 20 and below
2024-04-03 13:05 UTC
[PATCH 00/11] drm/i915/dp: Few MTL/DSC and a UHBR monitor fix
2024-04-03 12:10 UTC (4+ messages)
` [PATCH 01/11] drm/i915/dp: Fix DSC line buffer depth programming
[PATCH 00/25] Enable dislay support for Battlemage
2024-04-03 11:02 UTC (28+ messages)
` [PATCH 01/25] drm/i915/display: Prepare to handle new C20 PLL register address
` [PATCH 02/25] drm/xe/bmg: Add BMG platform definition
` [PATCH 03/25] drm/xe/bmg: Define IS_BATTLEMAGE macro
` [PATCH 04/25] drm/i915/bmg: "
` [PATCH 05/25] drm/i915/xe2: Skip CCS modifiers for Xe2 platforms
` [PATCH 06/25] drm/i915/xe2hpd: Initial cdclk table
` [PATCH 07/25] Revert "drm/i915/dgfx: DGFX uses direct VBT pin mapping"
` [PATCH 08/25] drm/i915/bmg: Extend DG2 tc check to future
` [PATCH 09/25] drm/i915/xe2hpd: Properly disable power in port A
` [PATCH 10/25] drm/i915/xe2hpd: Add new C20 PLL register address
` [PATCH 11/25] drm/i915/xe2hpd: Add support for eDP PLL configuration
` [PATCH 12/25] drm/i915/xe2hpd: update pll values in sync with Bspec
` [PATCH 13/25] drm/i915/xe2hpd: Add display info
` [PATCH 14/25] drm/i915/xe2hpd: Add missing chicken bit register programming
` [PATCH 15/25] drm/xe/display: Lane reversal requires writes to both context lanes
` [PATCH 16/25] drm/xe/xe2hpd: Define a new DRAM type INTEL_DRAM_GDDR
` [PATCH 17/25] drm/i915/xe2hpd: Add max memory bandwidth algorithm
` [PATCH 18/25] drm/i915/display: Enable RM timeout detection
` [PATCH 19/25] drm/i915/xe2hpd: Do not program MBUS_DBOX BW credits
` [PATCH 20/25] drm/i915/bmg: BMG should re-use MTL's south display logic
` [PATCH 21/25] drm/i915/xe2hpd: Set maximum DP rate to UHBR13.5
` [PATCH 22/25] drm/xe/gt_print: add xe_gt_err_once()
` [PATCH 23/25] drm/xe/device: implement transient flush
` [PATCH 24/25] drm/i915/display: perform "
` [PATCH 25/25] drm/xe/bmg: Enable the display support
` ✗ Fi.CI.BUILD: failure for Enable dislay support for Battlemage
[CI 1/3] drm: Add drm_vblank_work_flush_all()
2024-04-03 9:51 UTC (2+ messages)
` ✗ Fi.CI.BUILD: failure for series starting with [CI,1/3] drm: Add drm_vblank_work_flush_all(). (rev2)
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